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intel/elk: Remove encoding for Gfx9+

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Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
This commit is contained in:
Caio Oliveira
2024-02-09 23:57:23 -08:00
committed by Marge Bot
parent accac95c0d
commit 37cd18e30e
5 changed files with 351 additions and 1216 deletions
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228
src/intel/compiler/elk/elk_disasm.c
View File

@@ -1012,15 +1012,11 @@ dest_3src(FILE *file, const struct intel_device_info *devinfo,
unsigned subreg_nr;
enum elk_reg_type type;
if (devinfo->ver < 10 && is_align1)
if (is_align1)
return 0;
if (devinfo->ver == 6 && elk_inst_3src_a16_dst_reg_file(devinfo, inst))
reg_file = ELK_MESSAGE_REGISTER_FILE;
else if (devinfo->ver >= 12)
reg_file = elk_inst_3src_a1_dst_reg_file(devinfo, inst);
else if (is_align1 && elk_inst_3src_a1_dst_reg_file(devinfo, inst))
reg_file = ELK_ARCHITECTURE_REGISTER_FILE;
else
reg_file = ELK_GENERAL_REGISTER_FILE;
@@ -1028,13 +1024,8 @@ dest_3src(FILE *file, const struct intel_device_info *devinfo,
if (err == -1)
return 0;
if (is_align1) {
type = elk_inst_3src_a1_dst_type(devinfo, inst);
subreg_nr = elk_inst_3src_a1_dst_subreg_nr(devinfo, inst);
} else {
type = elk_inst_3src_a16_dst_type(devinfo, inst);
subreg_nr = elk_inst_3src_a16_dst_subreg_nr(devinfo, inst) * 4;
}
type = elk_inst_3src_a16_dst_type(devinfo, inst);
subreg_nr = elk_inst_3src_a16_dst_subreg_nr(devinfo, inst) * 4;
subreg_nr /= elk_reg_type_to_size(type);
if (subreg_nr)
@@ -1289,57 +1280,24 @@ src0_3src(FILE *file, const struct intel_device_info *devinfo,
bool is_scalar_region;
bool is_align1 = elk_inst_3src_access_mode(devinfo, inst) == ELK_ALIGN_1;
if (devinfo->ver < 10 && is_align1)
if (is_align1)
return 0;
if (is_align1) {
if (devinfo->ver >= 12 && !elk_inst_3src_a1_src0_is_imm(devinfo, inst)) {
_file = elk_inst_3src_a1_src0_reg_file(devinfo, inst);
} else if (elk_inst_3src_a1_src0_reg_file(devinfo, inst) ==
ELK_ALIGN1_3SRC_GENERAL_REGISTER_FILE) {
_file = ELK_GENERAL_REGISTER_FILE;
} else if (elk_inst_3src_a1_src0_type(devinfo, inst) ==
ELK_REGISTER_TYPE_NF) {
_file = ELK_ARCHITECTURE_REGISTER_FILE;
} else {
_file = ELK_IMMEDIATE_VALUE;
uint16_t imm_val = elk_inst_3src_a1_src0_imm(devinfo, inst);
enum elk_reg_type type = elk_inst_3src_a1_src0_type(devinfo, inst);
_file = ELK_GENERAL_REGISTER_FILE;
reg_nr = elk_inst_3src_src0_reg_nr(devinfo, inst);
subreg_nr = elk_inst_3src_a16_src0_subreg_nr(devinfo, inst) * 4;
type = elk_inst_3src_a16_src_type(devinfo, inst);
if (type == ELK_REGISTER_TYPE_W) {
format(file, "%dW", imm_val);
} else if (type == ELK_REGISTER_TYPE_UW) {
format(file, "0x%04xUW", imm_val);
} else if (type == ELK_REGISTER_TYPE_HF) {
format(file, "0x%04xHF", imm_val);
}
return 0;
}
reg_nr = elk_inst_3src_src0_reg_nr(devinfo, inst);
subreg_nr = elk_inst_3src_a1_src0_subreg_nr(devinfo, inst);
type = elk_inst_3src_a1_src0_type(devinfo, inst);
_vert_stride = vstride_from_align1_3src_vstride(
devinfo, elk_inst_3src_a1_src0_vstride(devinfo, inst));
_horiz_stride = hstride_from_align1_3src_hstride(
elk_inst_3src_a1_src0_hstride(devinfo, inst));
_width = implied_width(_vert_stride, _horiz_stride);
if (elk_inst_3src_a16_src0_rep_ctrl(devinfo, inst)) {
_vert_stride = ELK_VERTICAL_STRIDE_0;
_width = ELK_WIDTH_1;
_horiz_stride = ELK_HORIZONTAL_STRIDE_0;
} else {
_file = ELK_GENERAL_REGISTER_FILE;
reg_nr = elk_inst_3src_src0_reg_nr(devinfo, inst);
subreg_nr = elk_inst_3src_a16_src0_subreg_nr(devinfo, inst) * 4;
type = elk_inst_3src_a16_src_type(devinfo, inst);
if (elk_inst_3src_a16_src0_rep_ctrl(devinfo, inst)) {
_vert_stride = ELK_VERTICAL_STRIDE_0;
_width = ELK_WIDTH_1;
_horiz_stride = ELK_HORIZONTAL_STRIDE_0;
} else {
_vert_stride = ELK_VERTICAL_STRIDE_4;
_width = ELK_WIDTH_4;
_horiz_stride = ELK_HORIZONTAL_STRIDE_1;
}
_vert_stride = ELK_VERTICAL_STRIDE_4;
_width = ELK_WIDTH_4;
_horiz_stride = ELK_HORIZONTAL_STRIDE_1;
}
is_scalar_region = _vert_stride == ELK_VERTICAL_STRIDE_0 &&
_width == ELK_WIDTH_1 &&
_horiz_stride == ELK_HORIZONTAL_STRIDE_0;
@@ -1376,44 +1334,24 @@ src1_3src(FILE *file, const struct intel_device_info *devinfo,
bool is_scalar_region;
bool is_align1 = elk_inst_3src_access_mode(devinfo, inst) == ELK_ALIGN_1;
if (devinfo->ver < 10 && is_align1)
if (is_align1)
return 0;
if (is_align1) {
if (devinfo->ver >= 12) {
_file = elk_inst_3src_a1_src1_reg_file(devinfo, inst);
} else if (elk_inst_3src_a1_src1_reg_file(devinfo, inst) ==
ELK_ALIGN1_3SRC_GENERAL_REGISTER_FILE) {
_file = ELK_GENERAL_REGISTER_FILE;
} else {
_file = ELK_ARCHITECTURE_REGISTER_FILE;
}
_file = ELK_GENERAL_REGISTER_FILE;
reg_nr = elk_inst_3src_src1_reg_nr(devinfo, inst);
subreg_nr = elk_inst_3src_a16_src1_subreg_nr(devinfo, inst) * 4;
type = elk_inst_3src_a16_src_type(devinfo, inst);
reg_nr = elk_inst_3src_src1_reg_nr(devinfo, inst);
subreg_nr = elk_inst_3src_a1_src1_subreg_nr(devinfo, inst);
type = elk_inst_3src_a1_src1_type(devinfo, inst);
_vert_stride = vstride_from_align1_3src_vstride(
devinfo, elk_inst_3src_a1_src1_vstride(devinfo, inst));
_horiz_stride = hstride_from_align1_3src_hstride(
elk_inst_3src_a1_src1_hstride(devinfo, inst));
_width = implied_width(_vert_stride, _horiz_stride);
if (elk_inst_3src_a16_src1_rep_ctrl(devinfo, inst)) {
_vert_stride = ELK_VERTICAL_STRIDE_0;
_width = ELK_WIDTH_1;
_horiz_stride = ELK_HORIZONTAL_STRIDE_0;
} else {
_file = ELK_GENERAL_REGISTER_FILE;
reg_nr = elk_inst_3src_src1_reg_nr(devinfo, inst);
subreg_nr = elk_inst_3src_a16_src1_subreg_nr(devinfo, inst) * 4;
type = elk_inst_3src_a16_src_type(devinfo, inst);
if (elk_inst_3src_a16_src1_rep_ctrl(devinfo, inst)) {
_vert_stride = ELK_VERTICAL_STRIDE_0;
_width = ELK_WIDTH_1;
_horiz_stride = ELK_HORIZONTAL_STRIDE_0;
} else {
_vert_stride = ELK_VERTICAL_STRIDE_4;
_width = ELK_WIDTH_4;
_horiz_stride = ELK_HORIZONTAL_STRIDE_1;
}
_vert_stride = ELK_VERTICAL_STRIDE_4;
_width = ELK_WIDTH_4;
_horiz_stride = ELK_HORIZONTAL_STRIDE_1;
}
is_scalar_region = _vert_stride == ELK_VERTICAL_STRIDE_0 &&
_width == ELK_WIDTH_1 &&
_horiz_stride == ELK_HORIZONTAL_STRIDE_0;
@@ -1450,58 +1388,24 @@ src2_3src(FILE *file, const struct intel_device_info *devinfo,
bool is_scalar_region;
bool is_align1 = elk_inst_3src_access_mode(devinfo, inst) == ELK_ALIGN_1;
if (devinfo->ver < 10 && is_align1)
if (is_align1)
return 0;
if (is_align1) {
if (devinfo->ver >= 12 && !elk_inst_3src_a1_src2_is_imm(devinfo, inst)) {
_file = elk_inst_3src_a1_src2_reg_file(devinfo, inst);
} else if (elk_inst_3src_a1_src2_reg_file(devinfo, inst) ==
ELK_ALIGN1_3SRC_GENERAL_REGISTER_FILE) {
_file = ELK_GENERAL_REGISTER_FILE;
} else {
_file = ELK_IMMEDIATE_VALUE;
uint16_t imm_val = elk_inst_3src_a1_src2_imm(devinfo, inst);
enum elk_reg_type type = elk_inst_3src_a1_src2_type(devinfo, inst);
_file = ELK_GENERAL_REGISTER_FILE;
reg_nr = elk_inst_3src_src2_reg_nr(devinfo, inst);
subreg_nr = elk_inst_3src_a16_src2_subreg_nr(devinfo, inst) * 4;
type = elk_inst_3src_a16_src_type(devinfo, inst);
if (type == ELK_REGISTER_TYPE_W) {
format(file, "%dW", imm_val);
} else if (type == ELK_REGISTER_TYPE_UW) {
format(file, "0x%04xUW", imm_val);
} else if (type == ELK_REGISTER_TYPE_HF) {
format(file, "0x%04xHF", imm_val);
}
return 0;
}
reg_nr = elk_inst_3src_src2_reg_nr(devinfo, inst);
subreg_nr = elk_inst_3src_a1_src2_subreg_nr(devinfo, inst);
type = elk_inst_3src_a1_src2_type(devinfo, inst);
/* FINISHME: No vertical stride on src2. Is using the hstride in place
* correct? Doesn't seem like it, since there's hstride=1 but
* no vstride=1.
*/
_vert_stride = vstride_from_align1_3src_hstride(
elk_inst_3src_a1_src2_hstride(devinfo, inst));
_horiz_stride = hstride_from_align1_3src_hstride(
elk_inst_3src_a1_src2_hstride(devinfo, inst));
_width = implied_width(_vert_stride, _horiz_stride);
if (elk_inst_3src_a16_src2_rep_ctrl(devinfo, inst)) {
_vert_stride = ELK_VERTICAL_STRIDE_0;
_width = ELK_WIDTH_1;
_horiz_stride = ELK_HORIZONTAL_STRIDE_0;
} else {
_file = ELK_GENERAL_REGISTER_FILE;
reg_nr = elk_inst_3src_src2_reg_nr(devinfo, inst);
subreg_nr = elk_inst_3src_a16_src2_subreg_nr(devinfo, inst) * 4;
type = elk_inst_3src_a16_src_type(devinfo, inst);
if (elk_inst_3src_a16_src2_rep_ctrl(devinfo, inst)) {
_vert_stride = ELK_VERTICAL_STRIDE_0;
_width = ELK_WIDTH_1;
_horiz_stride = ELK_HORIZONTAL_STRIDE_0;
} else {
_vert_stride = ELK_VERTICAL_STRIDE_4;
_width = ELK_WIDTH_4;
_horiz_stride = ELK_HORIZONTAL_STRIDE_1;
}
_vert_stride = ELK_VERTICAL_STRIDE_4;
_width = ELK_WIDTH_4;
_horiz_stride = ELK_HORIZONTAL_STRIDE_1;
}
is_scalar_region = _vert_stride == ELK_VERTICAL_STRIDE_0 &&
_width == ELK_WIDTH_1 &&
_horiz_stride == ELK_HORIZONTAL_STRIDE_0;
@@ -1772,12 +1676,7 @@ inst_has_type(const struct elk_isa_info *isa,
return true;
if (num_sources >= 3) {
if (elk_inst_3src_access_mode(devinfo, inst) == ELK_ALIGN_1)
return elk_inst_3src_a1_src0_type(devinfo, inst) == type ||
elk_inst_3src_a1_src1_type(devinfo, inst) == type ||
elk_inst_3src_a1_src2_type(devinfo, inst) == type;
else
return elk_inst_3src_a16_src_type(devinfo, inst) == type;
return elk_inst_3src_a16_src_type(devinfo, inst) == type;
} else if (num_sources == 2) {
return elk_inst_src0_type(devinfo, inst) == type ||
elk_inst_src1_type(devinfo, inst) == type;
@@ -1786,32 +1685,6 @@ inst_has_type(const struct elk_isa_info *isa,
}
}
static int
swsb(FILE *file, const struct elk_isa_info *isa, const elk_inst *inst)
{
const struct intel_device_info *devinfo = isa->devinfo;
const enum elk_opcode opcode = elk_inst_opcode(isa, inst);
const uint32_t x = elk_inst_swsb(devinfo, inst);
const bool is_unordered =
opcode == ELK_OPCODE_SEND || opcode == ELK_OPCODE_SENDC ||
opcode == ELK_OPCODE_MATH ||
(devinfo->has_64bit_float_via_math_pipe &&
inst_has_type(isa, inst, ELK_REGISTER_TYPE_DF));
const struct tgl_swsb swsb = tgl_swsb_decode(devinfo, is_unordered, x);
if (swsb.regdist)
format(file, " %s@%d",
(swsb.pipe == TGL_PIPE_FLOAT ? "F" :
swsb.pipe == TGL_PIPE_INT ? "I" :
swsb.pipe == TGL_PIPE_LONG ? "L" :
swsb.pipe == TGL_PIPE_ALL ? "A" : "" ),
swsb.regdist);
if (swsb.mode)
format(file, " $%d%s", swsb.sbid,
(swsb.mode & TGL_SBID_SET ? "" :
swsb.mode & TGL_SBID_DST ? ".dst" : ".src"));
return 0;
}
#ifdef DEBUG
static __attribute__((__unused__)) int
elk_disassemble_imm(const struct elk_isa_info *isa,
@@ -2356,10 +2229,6 @@ elk_disassemble_inst(FILE *file, const struct elk_isa_info *isa,
format(file, " dst_len = %u,", lsc_msg_desc_dest_len(devinfo, imm_desc));
format(file, " src0_len = %u,", lsc_msg_desc_src0_len(devinfo, imm_desc));
if (!elk_inst_send_sel_reg32_ex_desc(devinfo, inst))
format(file, " src1_len = %d",
elk_message_ex_desc_ex_mlen(devinfo, imm_ex_desc));
err |= control(file, "address_type", lsc_addr_surface_type,
lsc_msg_desc_addr_type(devinfo, imm_desc), &space);
format(file, " )");
@@ -2485,14 +2354,6 @@ elk_disassemble_inst(FILE *file, const struct elk_isa_info *isa,
if (space)
string(file, " ");
}
if (devinfo->verx10 >= 125 &&
elk_inst_send_sel_reg32_ex_desc(devinfo, inst) &&
elk_inst_send_ex_bso(devinfo, inst)) {
format(file, " src1_len = %u",
(unsigned) elk_inst_send_src1_len(devinfo, inst));
format(file, " ex_bso");
}
if (elk_sfid_is_lsc(sfid) ||
(sfid == ELK_SFID_URB && devinfo->ver >= 20)) {
lsc_disassemble_ex_desc(devinfo, imm_desc, imm_ex_desc, file);
@@ -2541,9 +2402,6 @@ elk_disassemble_inst(FILE *file, const struct elk_isa_info *isa,
}
}
if (devinfo->ver >= 12)
err |= swsb(file, isa, inst);
err |= control(file, "compaction", cmpt_ctrl, is_compacted, &space);
err |= control(file, "thread control", thread_ctrl,
(devinfo->ver >= 12 ? elk_inst_atomic_control(devinfo, inst) :

251
src/intel/compiler/elk/elk_eu_emit.c
View File

@@ -421,8 +421,6 @@ elk_set_desc_ex(struct elk_codegen *p, elk_inst *inst,
elk_inst_set_src1_file_type(devinfo, inst,
ELK_IMMEDIATE_VALUE, ELK_REGISTER_TYPE_UD);
elk_inst_set_send_desc(devinfo, inst, desc);
if (devinfo->ver >= 9)
elk_inst_set_send_ex_desc(devinfo, inst, ex_desc);
}
static void elk_set_math_message( struct elk_codegen *p,
@@ -580,8 +578,6 @@ elk_inst_set_state(const struct elk_isa_info *isa,
elk_inst_set_compression(devinfo, insn, state->compressed);
elk_inst_set_access_mode(devinfo, insn, state->access_mode);
elk_inst_set_mask_control(devinfo, insn, state->mask_control);
if (devinfo->ver >= 12)
elk_inst_set_swsb(devinfo, insn, tgl_swsb_encode(devinfo, state->swsb));
elk_inst_set_saturate(devinfo, insn, state->saturate);
elk_inst_set_pred_control(devinfo, insn, state->predicate);
elk_inst_set_pred_inv(devinfo, insn, state->pred_inv);
@@ -784,192 +780,73 @@ elk_alu3(struct elk_codegen *p, unsigned opcode, struct elk_reg dest,
assert(src1.address_mode == ELK_ADDRESS_DIRECT);
assert(src2.address_mode == ELK_ADDRESS_DIRECT);
if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) {
assert(dest.file == ELK_GENERAL_REGISTER_FILE ||
(dest.file == ELK_ARCHITECTURE_REGISTER_FILE &&
dest.nr == ELK_ARF_ACCUMULATOR));
assert(dest.file == ELK_GENERAL_REGISTER_FILE ||
dest.file == ELK_MESSAGE_REGISTER_FILE);
assert(dest.type == ELK_REGISTER_TYPE_F ||
dest.type == ELK_REGISTER_TYPE_DF ||
dest.type == ELK_REGISTER_TYPE_D ||
dest.type == ELK_REGISTER_TYPE_UD ||
(dest.type == ELK_REGISTER_TYPE_HF && devinfo->ver >= 8));
if (devinfo->ver == 6) {
elk_inst_set_3src_a16_dst_reg_file(devinfo, inst,
dest.file == ELK_MESSAGE_REGISTER_FILE);
}
elk_inst_set_3src_dst_reg_nr(devinfo, inst, dest.nr);
elk_inst_set_3src_a16_dst_subreg_nr(devinfo, inst, dest.subnr / 4);
elk_inst_set_3src_a16_dst_writemask(devinfo, inst, dest.writemask);
if (devinfo->ver >= 12) {
elk_inst_set_3src_a1_dst_reg_file(devinfo, inst, dest.file);
elk_inst_set_3src_dst_reg_nr(devinfo, inst, phys_nr(devinfo, dest));
} else {
if (dest.file == ELK_ARCHITECTURE_REGISTER_FILE) {
elk_inst_set_3src_a1_dst_reg_file(devinfo, inst,
ELK_ALIGN1_3SRC_ACCUMULATOR);
elk_inst_set_3src_dst_reg_nr(devinfo, inst, ELK_ARF_ACCUMULATOR);
} else {
elk_inst_set_3src_a1_dst_reg_file(devinfo, inst,
ELK_ALIGN1_3SRC_GENERAL_REGISTER_FILE);
elk_inst_set_3src_dst_reg_nr(devinfo, inst, dest.nr);
}
}
elk_inst_set_3src_a1_dst_subreg_nr(devinfo, inst, phys_subnr(devinfo, dest) / 8);
assert(src0.file == ELK_GENERAL_REGISTER_FILE);
elk_inst_set_3src_a16_src0_swizzle(devinfo, inst, src0.swizzle);
elk_inst_set_3src_a16_src0_subreg_nr(devinfo, inst, get_3src_subreg_nr(src0));
elk_inst_set_3src_src0_reg_nr(devinfo, inst, src0.nr);
elk_inst_set_3src_src0_abs(devinfo, inst, src0.abs);
elk_inst_set_3src_src0_negate(devinfo, inst, src0.negate);
elk_inst_set_3src_a16_src0_rep_ctrl(devinfo, inst,
src0.vstride == ELK_VERTICAL_STRIDE_0);
elk_inst_set_3src_a1_dst_hstride(devinfo, inst, ELK_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1);
assert(src1.file == ELK_GENERAL_REGISTER_FILE);
elk_inst_set_3src_a16_src1_swizzle(devinfo, inst, src1.swizzle);
elk_inst_set_3src_a16_src1_subreg_nr(devinfo, inst, get_3src_subreg_nr(src1));
elk_inst_set_3src_src1_reg_nr(devinfo, inst, src1.nr);
elk_inst_set_3src_src1_abs(devinfo, inst, src1.abs);
elk_inst_set_3src_src1_negate(devinfo, inst, src1.negate);
elk_inst_set_3src_a16_src1_rep_ctrl(devinfo, inst,
src1.vstride == ELK_VERTICAL_STRIDE_0);
if (elk_reg_type_is_floating_point(dest.type)) {
elk_inst_set_3src_a1_exec_type(devinfo, inst,
ELK_ALIGN1_3SRC_EXEC_TYPE_FLOAT);
} else {
elk_inst_set_3src_a1_exec_type(devinfo, inst,
ELK_ALIGN1_3SRC_EXEC_TYPE_INT);
}
assert(src2.file == ELK_GENERAL_REGISTER_FILE);
elk_inst_set_3src_a16_src2_swizzle(devinfo, inst, src2.swizzle);
elk_inst_set_3src_a16_src2_subreg_nr(devinfo, inst, get_3src_subreg_nr(src2));
elk_inst_set_3src_src2_reg_nr(devinfo, inst, src2.nr);
elk_inst_set_3src_src2_abs(devinfo, inst, src2.abs);
elk_inst_set_3src_src2_negate(devinfo, inst, src2.negate);
elk_inst_set_3src_a16_src2_rep_ctrl(devinfo, inst,
src2.vstride == ELK_VERTICAL_STRIDE_0);
elk_inst_set_3src_a1_dst_type(devinfo, inst, dest.type);
elk_inst_set_3src_a1_src0_type(devinfo, inst, src0.type);
elk_inst_set_3src_a1_src1_type(devinfo, inst, src1.type);
elk_inst_set_3src_a1_src2_type(devinfo, inst, src2.type);
if (devinfo->ver >= 7) {
/* Set both the source and destination types based on dest.type,
* ignoring the source register types. The MAD and LRP emitters ensure
* that all four types are float. The BFE and BFI2 emitters, however,
* may send us mixed D and UD types and want us to ignore that and use
* the destination type.
*/
elk_inst_set_3src_a16_src_type(devinfo, inst, dest.type);
elk_inst_set_3src_a16_dst_type(devinfo, inst, dest.type);
if (src0.file == ELK_IMMEDIATE_VALUE) {
elk_inst_set_3src_a1_src0_imm(devinfo, inst, src0.ud);
} else {
elk_inst_set_3src_a1_src0_vstride(
devinfo, inst, to_3src_align1_vstride(devinfo, src0.vstride));
elk_inst_set_3src_a1_src0_hstride(devinfo, inst,
to_3src_align1_hstride(src0.hstride));
elk_inst_set_3src_a1_src0_subreg_nr(devinfo, inst, phys_subnr(devinfo, src0));
if (src0.type == ELK_REGISTER_TYPE_NF) {
elk_inst_set_3src_src0_reg_nr(devinfo, inst, ELK_ARF_ACCUMULATOR);
} else {
elk_inst_set_3src_src0_reg_nr(devinfo, inst, phys_nr(devinfo, src0));
}
elk_inst_set_3src_src0_abs(devinfo, inst, src0.abs);
elk_inst_set_3src_src0_negate(devinfo, inst, src0.negate);
}
elk_inst_set_3src_a1_src1_vstride(
devinfo, inst, to_3src_align1_vstride(devinfo, src1.vstride));
elk_inst_set_3src_a1_src1_hstride(devinfo, inst,
to_3src_align1_hstride(src1.hstride));
/* From the Bspec, 3D Media GPGPU, Instruction fields, srcType:
*
* "Three source instructions can use operands with mixed-mode
* precision. When SrcType field is set to :f or :hf it defines
* precision for source 0 only, and fields Src1Type and Src2Type
* define precision for other source operands:
*
* 0b = :f. Single precision Float (32-bit).
* 1b = :hf. Half precision Float (16-bit)."
*/
if (src1.type == ELK_REGISTER_TYPE_HF)
elk_inst_set_3src_a16_src1_type(devinfo, inst, 1);
elk_inst_set_3src_a1_src1_subreg_nr(devinfo, inst, phys_subnr(devinfo, src1));
if (src1.file == ELK_ARCHITECTURE_REGISTER_FILE) {
elk_inst_set_3src_src1_reg_nr(devinfo, inst, ELK_ARF_ACCUMULATOR);
} else {
elk_inst_set_3src_src1_reg_nr(devinfo, inst, phys_nr(devinfo, src1));
}
elk_inst_set_3src_src1_abs(devinfo, inst, src1.abs);
elk_inst_set_3src_src1_negate(devinfo, inst, src1.negate);
if (src2.file == ELK_IMMEDIATE_VALUE) {
elk_inst_set_3src_a1_src2_imm(devinfo, inst, src2.ud);
} else {
elk_inst_set_3src_a1_src2_hstride(devinfo, inst,
to_3src_align1_hstride(src2.hstride));
/* no vstride on src2 */
elk_inst_set_3src_a1_src2_subreg_nr(devinfo, inst, phys_subnr(devinfo, src2));
elk_inst_set_3src_src2_reg_nr(devinfo, inst, phys_nr(devinfo, src2));
elk_inst_set_3src_src2_abs(devinfo, inst, src2.abs);
elk_inst_set_3src_src2_negate(devinfo, inst, src2.negate);
}
assert(src0.file == ELK_GENERAL_REGISTER_FILE ||
src0.file == ELK_IMMEDIATE_VALUE ||
(src0.file == ELK_ARCHITECTURE_REGISTER_FILE &&
src0.type == ELK_REGISTER_TYPE_NF));
assert(src1.file == ELK_GENERAL_REGISTER_FILE ||
(src1.file == ELK_ARCHITECTURE_REGISTER_FILE &&
src1.nr == ELK_ARF_ACCUMULATOR));
assert(src2.file == ELK_GENERAL_REGISTER_FILE ||
src2.file == ELK_IMMEDIATE_VALUE);
if (devinfo->ver >= 12) {
if (src0.file == ELK_IMMEDIATE_VALUE) {
elk_inst_set_3src_a1_src0_is_imm(devinfo, inst, 1);
} else {
elk_inst_set_3src_a1_src0_reg_file(devinfo, inst, src0.file);
}
elk_inst_set_3src_a1_src1_reg_file(devinfo, inst, src1.file);
if (src2.file == ELK_IMMEDIATE_VALUE) {
elk_inst_set_3src_a1_src2_is_imm(devinfo, inst, 1);
} else {
elk_inst_set_3src_a1_src2_reg_file(devinfo, inst, src2.file);
}
} else {
elk_inst_set_3src_a1_src0_reg_file(devinfo, inst,
src0.file == ELK_GENERAL_REGISTER_FILE ?
ELK_ALIGN1_3SRC_GENERAL_REGISTER_FILE :
ELK_ALIGN1_3SRC_IMMEDIATE_VALUE);
elk_inst_set_3src_a1_src1_reg_file(devinfo, inst,
src1.file == ELK_GENERAL_REGISTER_FILE ?
ELK_ALIGN1_3SRC_GENERAL_REGISTER_FILE :
ELK_ALIGN1_3SRC_ACCUMULATOR);
elk_inst_set_3src_a1_src2_reg_file(devinfo, inst,
src2.file == ELK_GENERAL_REGISTER_FILE ?
ELK_ALIGN1_3SRC_GENERAL_REGISTER_FILE :
ELK_ALIGN1_3SRC_IMMEDIATE_VALUE);
}
} else {
assert(dest.file == ELK_GENERAL_REGISTER_FILE ||
dest.file == ELK_MESSAGE_REGISTER_FILE);
assert(dest.type == ELK_REGISTER_TYPE_F ||
dest.type == ELK_REGISTER_TYPE_DF ||
dest.type == ELK_REGISTER_TYPE_D ||
dest.type == ELK_REGISTER_TYPE_UD ||
(dest.type == ELK_REGISTER_TYPE_HF && devinfo->ver >= 8));
if (devinfo->ver == 6) {
elk_inst_set_3src_a16_dst_reg_file(devinfo, inst,
dest.file == ELK_MESSAGE_REGISTER_FILE);
}
elk_inst_set_3src_dst_reg_nr(devinfo, inst, dest.nr);
elk_inst_set_3src_a16_dst_subreg_nr(devinfo, inst, dest.subnr / 4);
elk_inst_set_3src_a16_dst_writemask(devinfo, inst, dest.writemask);
assert(src0.file == ELK_GENERAL_REGISTER_FILE);
elk_inst_set_3src_a16_src0_swizzle(devinfo, inst, src0.swizzle);
elk_inst_set_3src_a16_src0_subreg_nr(devinfo, inst, get_3src_subreg_nr(src0));
elk_inst_set_3src_src0_reg_nr(devinfo, inst, src0.nr);
elk_inst_set_3src_src0_abs(devinfo, inst, src0.abs);
elk_inst_set_3src_src0_negate(devinfo, inst, src0.negate);
elk_inst_set_3src_a16_src0_rep_ctrl(devinfo, inst,
src0.vstride == ELK_VERTICAL_STRIDE_0);
assert(src1.file == ELK_GENERAL_REGISTER_FILE);
elk_inst_set_3src_a16_src1_swizzle(devinfo, inst, src1.swizzle);
elk_inst_set_3src_a16_src1_subreg_nr(devinfo, inst, get_3src_subreg_nr(src1));
elk_inst_set_3src_src1_reg_nr(devinfo, inst, src1.nr);
elk_inst_set_3src_src1_abs(devinfo, inst, src1.abs);
elk_inst_set_3src_src1_negate(devinfo, inst, src1.negate);
elk_inst_set_3src_a16_src1_rep_ctrl(devinfo, inst,
src1.vstride == ELK_VERTICAL_STRIDE_0);
assert(src2.file == ELK_GENERAL_REGISTER_FILE);
elk_inst_set_3src_a16_src2_swizzle(devinfo, inst, src2.swizzle);
elk_inst_set_3src_a16_src2_subreg_nr(devinfo, inst, get_3src_subreg_nr(src2));
elk_inst_set_3src_src2_reg_nr(devinfo, inst, src2.nr);
elk_inst_set_3src_src2_abs(devinfo, inst, src2.abs);
elk_inst_set_3src_src2_negate(devinfo, inst, src2.negate);
elk_inst_set_3src_a16_src2_rep_ctrl(devinfo, inst,
src2.vstride == ELK_VERTICAL_STRIDE_0);
if (devinfo->ver >= 7) {
/* Set both the source and destination types based on dest.type,
* ignoring the source register types. The MAD and LRP emitters ensure
* that all four types are float. The BFE and BFI2 emitters, however,
* may send us mixed D and UD types and want us to ignore that and use
* the destination type.
*/
elk_inst_set_3src_a16_src_type(devinfo, inst, dest.type);
elk_inst_set_3src_a16_dst_type(devinfo, inst, dest.type);
/* From the Bspec, 3D Media GPGPU, Instruction fields, srcType:
*
* "Three source instructions can use operands with mixed-mode
* precision. When SrcType field is set to :f or :hf it defines
* precision for source 0 only, and fields Src1Type and Src2Type
* define precision for other source operands:
*
* 0b = :f. Single precision Float (32-bit).
* 1b = :hf. Half precision Float (16-bit)."
*/
if (src1.type == ELK_REGISTER_TYPE_HF)
elk_inst_set_3src_a16_src1_type(devinfo, inst, 1);
if (src2.type == ELK_REGISTER_TYPE_HF)
elk_inst_set_3src_a16_src2_type(devinfo, inst, 1);
}
if (src2.type == ELK_REGISTER_TYPE_HF)
elk_inst_set_3src_a16_src2_type(devinfo, inst, 1);
}
return inst;
@@ -2672,11 +2549,7 @@ elk_send_indirect_message(struct elk_codegen *p,
elk_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1));
send = next_insn(p, ELK_OPCODE_SEND);
elk_set_src0(p, send, retype(payload, ELK_REGISTER_TYPE_UD));
if (devinfo->ver >= 12)
elk_inst_set_send_sel_reg32_desc(devinfo, send, true);
else
elk_set_src1(p, send, addr);
elk_set_src1(p, send, addr);
}
elk_set_dest(p, send, dst);

86
src/intel/compiler/elk/elk_eu_validate.c
View File

@@ -261,15 +261,7 @@ invalid_values(const struct elk_isa_info *isa, const elk_inst *inst)
if (num_sources == 3) {
if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) {
if (devinfo->ver >= 10) {
ERROR_IF(elk_inst_3src_a1_dst_type (devinfo, inst) == INVALID_REG_TYPE ||
elk_inst_3src_a1_src0_type(devinfo, inst) == INVALID_REG_TYPE ||
elk_inst_3src_a1_src1_type(devinfo, inst) == INVALID_REG_TYPE ||
elk_inst_3src_a1_src2_type(devinfo, inst) == INVALID_REG_TYPE,
"invalid register type encoding");
} else {
ERROR("Align1 mode not allowed on Gen < 10");
}
ERROR("Align1 mode not allowed on Gen < 10");
} else {
ERROR_IF(elk_inst_3src_a16_dst_type(devinfo, inst) == INVALID_REG_TYPE ||
elk_inst_3src_a16_src_type(devinfo, inst) == INVALID_REG_TYPE,
@@ -638,27 +630,10 @@ general_restrictions_based_on_operand_types(const struct elk_isa_info *isa,
if (inst_is_send(isa, inst))
return error_msg;
if (devinfo->ver >= 11) {
if (num_sources == 3) {
ERROR_IF(elk_reg_type_to_size(elk_inst_3src_a1_src1_type(devinfo, inst)) == 1 ||
elk_reg_type_to_size(elk_inst_3src_a1_src2_type(devinfo, inst)) == 1,
"Byte data type is not supported for src1/2 register regioning. This includes "
"byte broadcast as well.");
}
if (num_sources == 2) {
ERROR_IF(elk_reg_type_to_size(elk_inst_src1_type(devinfo, inst)) == 1,
"Byte data type is not supported for src1 register regioning. This includes "
"byte broadcast as well.");
}
}
enum elk_reg_type dst_type;
if (num_sources == 3) {
if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1)
dst_type = elk_inst_3src_a1_dst_type(devinfo, inst);
else
dst_type = elk_inst_3src_a16_dst_type(devinfo, inst);
dst_type = elk_inst_3src_a16_dst_type(devinfo, inst);
} else {
dst_type = inst_dst_type(isa, inst);
}
@@ -675,16 +650,7 @@ general_restrictions_based_on_operand_types(const struct elk_isa_info *isa,
for (unsigned s = 0; s < num_sources; s++) {
enum elk_reg_type src_type;
if (num_sources == 3) {
if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) {
switch (s) {
case 0: src_type = elk_inst_3src_a1_src0_type(devinfo, inst); break;
case 1: src_type = elk_inst_3src_a1_src1_type(devinfo, inst); break;
case 2: src_type = elk_inst_3src_a1_src2_type(devinfo, inst); break;
default: unreachable("invalid src");
}
} else {
src_type = elk_inst_3src_a16_src_type(devinfo, inst);
}
src_type = elk_inst_3src_a16_src_type(devinfo, inst);
} else {
switch (s) {
case 0: src_type = elk_inst_src0_type(devinfo, inst); break;
@@ -2281,30 +2247,17 @@ instruction_restrictions(const struct elk_isa_info *isa,
ERROR_IF(elk_inst_saturate(devinfo, inst),
"BFI2 cannot have saturate modifier");
enum elk_reg_type dst_type;
ERROR_IF(elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1,
"BFI2 cannot have Align1");
if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1)
dst_type = elk_inst_3src_a1_dst_type(devinfo, inst);
else
dst_type = elk_inst_3src_a16_dst_type(devinfo, inst);
enum elk_reg_type dst_type = elk_inst_3src_a16_dst_type(devinfo, inst);
ERROR_IF(dst_type != ELK_REGISTER_TYPE_D &&
dst_type != ELK_REGISTER_TYPE_UD,
"BFI2 destination type must be D or UD");
for (unsigned s = 0; s < 3; s++) {
enum elk_reg_type src_type;
if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) {
switch (s) {
case 0: src_type = elk_inst_3src_a1_src0_type(devinfo, inst); break;
case 1: src_type = elk_inst_3src_a1_src1_type(devinfo, inst); break;
case 2: src_type = elk_inst_3src_a1_src2_type(devinfo, inst); break;
default: unreachable("invalid src");
}
} else {
src_type = elk_inst_3src_a16_src_type(devinfo, inst);
}
enum elk_reg_type src_type = elk_inst_3src_a16_src_type(devinfo, inst);
ERROR_IF(src_type != dst_type,
"BFI2 source type must match destination type");
@@ -2321,18 +2274,12 @@ instruction_restrictions(const struct elk_isa_info *isa,
ERROR_IF(elk_inst_cond_modifier(devinfo, inst) == ELK_CONDITIONAL_NONE,
"CSEL must have a condition.");
enum elk_reg_type dst_type;
if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1)
dst_type = elk_inst_3src_a1_dst_type(devinfo, inst);
else
dst_type = elk_inst_3src_a16_dst_type(devinfo, inst);
ERROR_IF(elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1,
"CSEL cannot have Align1.");
enum elk_reg_type dst_type = elk_inst_3src_a16_dst_type(devinfo, inst);
if (devinfo->ver < 8) {
ERROR_IF(devinfo->ver < 8, "CSEL not supported before Gfx8");
} else if (devinfo->ver <= 9) {
ERROR_IF(dst_type != ELK_REGISTER_TYPE_F,
"CSEL destination type must be F");
} else {
ERROR_IF(dst_type != ELK_REGISTER_TYPE_F &&
dst_type != ELK_REGISTER_TYPE_HF &&
@@ -2342,18 +2289,7 @@ instruction_restrictions(const struct elk_isa_info *isa,
}
for (unsigned s = 0; s < 3; s++) {
enum elk_reg_type src_type;
if (elk_inst_access_mode(devinfo, inst) == ELK_ALIGN_1) {
switch (s) {
case 0: src_type = elk_inst_3src_a1_src0_type(devinfo, inst); break;
case 1: src_type = elk_inst_3src_a1_src1_type(devinfo, inst); break;
case 2: src_type = elk_inst_3src_a1_src2_type(devinfo, inst); break;
default: unreachable("invalid src");
}
} else {
src_type = elk_inst_3src_a16_src_type(devinfo, inst);
}
enum elk_reg_type src_type = elk_inst_3src_a16_src_type(devinfo, inst);
ERROR_IF(src_type != dst_type,
"CSEL source type must match destination type");

17
src/intel/compiler/elk/elk_gram.y
View File

@@ -286,17 +286,12 @@ i965_asm_set_instruction_options(struct elk_codegen *p,
options.access_mode);
elk_inst_set_mask_control(p->devinfo, elk_last_inst,
options.mask_control);
if (p->devinfo->ver < 12) {
elk_inst_set_thread_control(p->devinfo, elk_last_inst,
options.thread_control);
elk_inst_set_no_dd_check(p->devinfo, elk_last_inst,
options.no_dd_check);
elk_inst_set_no_dd_clear(p->devinfo, elk_last_inst,
options.no_dd_clear);
} else {
elk_inst_set_swsb(p->devinfo, elk_last_inst,
tgl_swsb_encode(p->devinfo, options.depinfo));
}
elk_inst_set_thread_control(p->devinfo, elk_last_inst,
options.thread_control);
elk_inst_set_no_dd_check(p->devinfo, elk_last_inst,
options.no_dd_check);
elk_inst_set_no_dd_clear(p->devinfo, elk_last_inst,
options.no_dd_clear);
elk_inst_set_debug_control(p->devinfo, elk_last_inst,
options.debug_control);
if (p->devinfo->ver >= 6)

985
src/intel/compiler/elk/elk_inst.h
View File

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