nir: Don't manually index intrinsic index enum
This fixes a rebase fail in ea51275e07
, and prevents it from happening
again. There's no reason to do this manually.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
@@ -1209,80 +1209,80 @@ typedef enum {
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/**
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* For store instructions, a writemask for the store.
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*/
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NIR_INTRINSIC_WRMASK = 2,
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NIR_INTRINSIC_WRMASK,
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/**
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* The stream-id for GS emit_vertex/end_primitive intrinsics.
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*/
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NIR_INTRINSIC_STREAM_ID = 3,
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NIR_INTRINSIC_STREAM_ID,
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/**
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* The clip-plane id for load_user_clip_plane intrinsic.
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*/
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NIR_INTRINSIC_UCP_ID = 4,
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NIR_INTRINSIC_UCP_ID,
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/**
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* The amount of data, starting from BASE, that this instruction may
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* access. This is used to provide bounds if the offset is not constant.
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*/
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NIR_INTRINSIC_RANGE = 5,
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NIR_INTRINSIC_RANGE,
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/**
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* The Vulkan descriptor set for vulkan_resource_index intrinsic.
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*/
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NIR_INTRINSIC_DESC_SET = 6,
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NIR_INTRINSIC_DESC_SET,
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/**
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* The Vulkan descriptor set binding for vulkan_resource_index intrinsic.
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*/
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NIR_INTRINSIC_BINDING = 7,
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NIR_INTRINSIC_BINDING,
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/**
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* Component offset.
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*/
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NIR_INTRINSIC_COMPONENT = 8,
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NIR_INTRINSIC_COMPONENT,
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/**
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* Interpolation mode (only meaningful for FS inputs).
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*/
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NIR_INTRINSIC_INTERP_MODE = 9,
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NIR_INTRINSIC_INTERP_MODE,
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/**
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* A binary nir_op to use when performing a reduction or scan operation
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*/
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NIR_INTRINSIC_REDUCTION_OP = 10,
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NIR_INTRINSIC_REDUCTION_OP,
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/**
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* Cluster size for reduction operations
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*/
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NIR_INTRINSIC_CLUSTER_SIZE = 11,
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NIR_INTRINSIC_CLUSTER_SIZE,
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/**
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* Parameter index for a load_param intrinsic
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*/
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NIR_INTRINSIC_PARAM_IDX = 12,
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NIR_INTRINSIC_PARAM_IDX,
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/**
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* Image dimensionality for image intrinsics
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*
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* One of GLSL_SAMPLER_DIM_*
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*/
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NIR_INTRINSIC_IMAGE_DIM = 13,
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NIR_INTRINSIC_IMAGE_DIM,
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/**
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* Non-zero if we are accessing an array image
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*/
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NIR_INTRINSIC_IMAGE_ARRAY = 14,
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NIR_INTRINSIC_IMAGE_ARRAY,
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/**
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* Image format for image intrinsics
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*/
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NIR_INTRINSIC_FORMAT = 15,
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NIR_INTRINSIC_FORMAT,
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/**
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* Access qualifiers for image and memory access intrinsics
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*/
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NIR_INTRINSIC_ACCESS = 16,
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NIR_INTRINSIC_ACCESS,
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/**
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* Alignment for offsets and addresses
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@@ -1293,24 +1293,24 @@ typedef enum {
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*
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* (X - align_offset) % align_mul == 0
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*/
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NIR_INTRINSIC_ALIGN_MUL = 17,
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NIR_INTRINSIC_ALIGN_OFFSET = 18,
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NIR_INTRINSIC_ALIGN_MUL,
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NIR_INTRINSIC_ALIGN_OFFSET,
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/**
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* The Vulkan descriptor type for a vulkan_resource_[re]index intrinsic.
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*/
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NIR_INTRINSIC_DESC_TYPE = 19,
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NIR_INTRINSIC_DESC_TYPE,
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/**
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* The nir_alu_type of a uniform/input/output
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*/
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NIR_INTRINSIC_TYPE = 20,
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NIR_INTRINSIC_TYPE,
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/**
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* The swizzle mask for the instructions
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* SwizzleInvocationsAMD and SwizzleInvocationsMaskedAMD
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*/
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NIR_INTRINSIC_SWIZZLE_MASK = 20,
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NIR_INTRINSIC_SWIZZLE_MASK,
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NIR_INTRINSIC_NUM_INDEX_FLAGS,
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