From 37b88a72fb2ea510a284821c53f4484d9c622b45 Mon Sep 17 00:00:00 2001 From: Matt Turner Date: Wed, 30 Aug 2023 14:50:00 -0400 Subject: [PATCH] intel: Rearrange for next commit Part-of: --- meson.build | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/meson.build b/meson.build index 4b98666b914..e8448039d4b 100644 --- a/meson.build +++ b/meson.build @@ -251,6 +251,14 @@ with_any_broadcom = [ with_broadcom_vk, ].contains(true) +if ['x86_64'].contains(host_machine.cpu_family()) + with_intel_clc = get_option('intel-clc').enabled() + with_intel_vk_rt = with_intel_vk and with_intel_clc +else + with_intel_clc = false + with_intel_vk_rt = false +endif + with_any_intel = [ with_gallium_crocus, with_gallium_i915, @@ -278,13 +286,6 @@ if with_aco_tests and not with_amd_vk endif with_microsoft_clc = get_option('microsoft-clc').enabled() -if ['x86_64'].contains(host_machine.cpu_family()) - with_intel_clc = get_option('intel-clc').enabled() - with_intel_vk_rt = with_intel_vk and with_intel_clc -else - with_intel_clc = false - with_intel_vk_rt = false -endif with_clc = with_microsoft_clc or with_intel_clc with_spirv_to_dxil = get_option('spirv-to-dxil')