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nir/opt_peephole_select: Don't peephole_select expensive math instructions

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On some GPUs, especially older Intel GPUs, some math instructions are
very expensive.  On those architectures, don't reduce flow control to a
csel if one of the branches contains one of these expensive math
instructions.

This prevents a bunch of cycle count regressions on pre-Gen6 platforms
with a later patch (intel/compiler: More peephole select for pre-Gen6).

v2: Remove stray #if block.  Noticed by Thomas.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
This commit is contained in:
Ian Romanick
2018-06-18 16:11:55 -07:00
parent 8fb8ebfbb0
commit 378f996771
9 changed files with 40 additions and 17 deletions
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4
src/intel/compiler/brw_nir.c
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@@ -589,9 +589,9 @@ brw_nir_optimize(nir_shader *nir, const struct brw_compiler *compiler,
const bool is_vec4_tessellation = !is_scalar &&
(nir->info.stage == MESA_SHADER_TESS_CTRL ||
nir->info.stage == MESA_SHADER_TESS_EVAL);
OPT(nir_opt_peephole_select, 0, !is_vec4_tessellation);
OPT(nir_opt_peephole_select, 0, !is_vec4_tessellation, false);
if (compiler->devinfo->gen >= 6)
OPT(nir_opt_peephole_select, 1, !is_vec4_tessellation);
OPT(nir_opt_peephole_select, 1, !is_vec4_tessellation, true);
OPT(nir_opt_intrinsics);
OPT(nir_opt_idiv_const, 32);