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anv: move lowering of descriptor intrinsics to apply_layout

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30713>
This commit is contained in:
Lionel Landwerlin
2024-05-10 19:50:48 +03:00
committed by Marge Bot
parent 45117c0ed5
commit 3769b58272
2 changed files with 36 additions and 69 deletions
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39
src/intel/vulkan/anv_nir_apply_pipeline_layout.c
View File

@@ -546,6 +546,39 @@ build_load_storage_3d_image_depth(nir_builder *b,
return nir_umin(b, resinfo_depth, depth);
}
}
static nir_def *
build_load_desc_set_dynamic_index(nir_builder *b, unsigned set_idx)
{
return nir_iand_imm(
b,
anv_load_driver_uniform(b, 1, desc_surface_offsets[set_idx]),
ANV_DESCRIPTOR_SET_DYNAMIC_INDEX_MASK);
}
static nir_def *
build_load_desc_address(nir_builder *b, nir_def *set_idx, unsigned set_idx_imm,
const struct apply_pipeline_layout_state *state)
{
nir_def *desc_offset = set_idx != NULL ?
anv_load_driver_uniform_indexed(b, 1, desc_surface_offsets, set_idx) :
anv_load_driver_uniform(b, 1, desc_surface_offsets[set_idx_imm]);
desc_offset = nir_iand_imm(b, desc_offset, ANV_DESCRIPTOR_SET_OFFSET_MASK);
if (state->layout->type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_BUFFER &&
!state->pdevice->uses_ex_bso) {
nir_def *bindless_base_offset =
anv_load_driver_uniform(b, 1, surfaces_base_offset);
desc_offset = nir_iadd(b, bindless_base_offset, desc_offset);
}
return nir_pack_64_2x32_split(
b, desc_offset,
nir_load_reloc_const_intel(
b,
state->layout->type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_BUFFER ?
BRW_SHADER_RELOC_DESCRIPTORS_BUFFER_ADDR_HIGH :
BRW_SHADER_RELOC_DESCRIPTORS_ADDR_HIGH));
}
/** Build a Vulkan resource index
*
* A "resource index" is the term used by our SPIR-V parser and the relevant
@@ -605,7 +638,7 @@ build_res_index(nir_builder *b,
if (bind_layout->dynamic_offset_index >= 0) {
if (state->has_independent_sets) {
nir_def *dynamic_offset_start =
nir_load_desc_set_dynamic_index_intel(b, nir_imm_int(b, set));
build_load_desc_set_dynamic_index(b, set);
dynamic_offset_index =
nir_iadd_imm(b, dynamic_offset_start,
bind_layout->dynamic_offset_index);
@@ -740,7 +773,7 @@ build_desc_addr_for_res_index(nir_builder *b,
switch (state->desc_addr_format) {
case nir_address_format_64bit_global_32bit_offset: {
nir_def *base_addr =
nir_load_desc_set_address_intel(b, res.set_idx);
build_load_desc_address(b, res.set_idx, 0, state);
return nir_vec4(b, nir_unpack_64_2x32_split_x(b, base_addr),
nir_unpack_64_2x32_split_y(b, base_addr),
nir_imm_int(b, UINT32_MAX),
@@ -777,7 +810,7 @@ build_desc_addr_for_binding(nir_builder *b,
switch (state->desc_addr_format) {
case nir_address_format_64bit_global_32bit_offset:
case nir_address_format_64bit_bounded_global: {
nir_def *set_addr = nir_load_desc_set_address_intel(b, nir_imm_int(b, set));
nir_def *set_addr = build_load_desc_address(b, NULL, set, state);
nir_def *desc_offset =
nir_iadd_imm(b,
nir_imul_imm(b,

66
src/intel/vulkan/anv_nir_compute_push_layout.c
View File

@@ -65,25 +65,6 @@ anv_nir_compute_push_layout(nir_shader *nir,
break;
}
case nir_intrinsic_load_desc_set_address_intel:
case nir_intrinsic_load_desc_set_dynamic_index_intel: {
unsigned base = offsetof(struct anv_push_constants,
desc_surface_offsets);
push_start = MIN2(push_start, base);
push_end = MAX2(push_end, base +
anv_drv_const_size(desc_surface_offsets));
if (desc_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_BUFFER &&
!pdevice->uses_ex_bso) {
base = offsetof(struct anv_push_constants,
surfaces_base_offset);
push_start = MIN2(push_start, base);
push_end = MAX2(push_end, base +
anv_drv_const_size(surfaces_base_offset));
}
break;
}
default:
break;
}
@@ -153,9 +134,6 @@ anv_nir_compute_push_layout(nir_shader *nir,
if (has_push_intrinsic) {
nir_foreach_function_impl(impl, nir) {
nir_builder build = nir_builder_create(impl);
nir_builder *b = &build;
nir_foreach_block(block, impl) {
nir_foreach_instr_safe(instr, block) {
if (instr->type != nir_instr_type_intrinsic)
@@ -179,50 +157,6 @@ anv_nir_compute_push_layout(nir_shader *nir,
break;
}
case nir_intrinsic_load_desc_set_address_intel: {
assert(brw_shader_stage_requires_bindless_resources(nir->info.stage));
b->cursor = nir_before_instr(&intrin->instr);
nir_def *desc_offset = nir_load_uniform(b, 1, 32,
nir_imul_imm(b, intrin->src[0].ssa, sizeof(uint32_t)),
.base = anv_drv_const_offset(desc_surface_offsets),
.range = anv_drv_const_size(desc_surface_offsets),
.dest_type = nir_type_uint32);
desc_offset = nir_iand_imm(b, desc_offset, ANV_DESCRIPTOR_SET_OFFSET_MASK);
if (desc_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_BUFFER &&
!pdevice->uses_ex_bso) {
nir_def *bindless_base_offset = nir_load_uniform(
b, 1, 32,
nir_imm_int(b, 0),
.base = anv_drv_const_offset(surfaces_base_offset),
.range = anv_drv_const_size(surfaces_base_offset),
.dest_type = nir_type_uint32);
desc_offset = nir_iadd(b, bindless_base_offset, desc_offset);
}
nir_def *desc_addr =
nir_pack_64_2x32_split(
b, desc_offset,
nir_load_reloc_const_intel(
b,
desc_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_BUFFER ?
BRW_SHADER_RELOC_DESCRIPTORS_BUFFER_ADDR_HIGH :
BRW_SHADER_RELOC_DESCRIPTORS_ADDR_HIGH));
nir_def_rewrite_uses(&intrin->def, desc_addr);
break;
}
case nir_intrinsic_load_desc_set_dynamic_index_intel: {
b->cursor = nir_before_instr(&intrin->instr);
nir_def *pc_load = nir_load_uniform(b, 1, 32,
nir_imul_imm(b, intrin->src[0].ssa, sizeof(uint32_t)),
.base = anv_drv_const_offset(desc_surface_offsets),
.range = anv_drv_const_size(desc_surface_offsets),
.dest_type = nir_type_uint32);
pc_load = nir_iand_imm(
b, pc_load, ANV_DESCRIPTOR_SET_DYNAMIC_INDEX_MASK);
nir_def_rewrite_uses(&intrin->def, pc_load);
break;
}
default:
break;
}