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intel/fs: don't consider fixup_nomask_control_flow SENDs predicate

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Those SENDs are still doing a full register write. We just inserted
some predication for a workaround.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853>
This commit is contained in:
Lionel Landwerlin
2023-03-14 18:22:50 +02:00
committed by Marge Bot
parent 34d8bfe65f
commit 362a07db3a
2 changed files with 9 additions and 1 deletions
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4
src/intel/compiler/brw_fs.cpp
View File

@@ -641,7 +641,8 @@ fs_visitor::limit_dispatch_width(unsigned n, const char *msg)
bool
fs_inst::is_partial_write() const
{
if (this->predicate && this->opcode != BRW_OPCODE_SEL)
if (this->predicate && !this->predicate_trivial &&
this->opcode != BRW_OPCODE_SEL)
return true;
if (this->dst.offset % REG_SIZE != 0)
@@ -6453,6 +6454,7 @@ fs_visitor::fixup_nomask_control_flow()
set_predicate(pred, inst);
inst->flag_subreg = 0;
inst->predicate_trivial = true;
if (save_flag)
ubld.group(1, 0).at(block, inst->next).MOV(flag, tmp);

6
src/intel/compiler/brw_ir.h
View File

@@ -178,6 +178,12 @@ struct backend_instruction {
* the scratch surface offset to build
* extended descriptor
*/
bool predicate_trivial:1; /**< The predication mask applied to this
* instruction is guaranteed to be uniform and
* a superset of the execution mask of the
* present block, no currently enabled channels
* will be disabled by the predicate.
*/
bool eot:1;
/* Chooses which flag subregister (f0.0 to f1.1) is used for conditional