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radv/llvm: fix enabled_channels for compressed exports

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The old values seemed to work fine, but the ISA docs recommend 0x0,0x3,0xc
and 0xf:

COMPR==1: export half-dword enable. Valid values are: 0x0,3,c,f
[0] enables VSRC0 : R,G from one VGPR (R in low bits, G high)
[2] enables VSRC1 : B,A from one VGPR (B in low bits, A high)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9459>
This commit is contained in:
Rhys Perry
2021-03-11 11:40:51 +00:00
parent 341dd9d834
commit 35fe62dad1
1 changed files with 5 additions and 5 deletions
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10
src/amd/vulkan/radv_nir_to_llvm.c
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@@ -1433,7 +1433,7 @@ si_llvm_init_export_args(struct radv_shader_context *ctx,
break;
case V_028714_SPI_SHADER_FP16_ABGR:
args->enabled_channels = 0x5;
args->enabled_channels = 0xf;
packf = ac_build_cvt_pkrtz_f16;
if (is_16bit) {
for (unsigned chan = 0; chan < 4; chan++)
@@ -1444,17 +1444,17 @@ si_llvm_init_export_args(struct radv_shader_context *ctx,
break;
case V_028714_SPI_SHADER_UNORM16_ABGR:
args->enabled_channels = 0x5;
args->enabled_channels = 0xf;
packf = ac_build_cvt_pknorm_u16;
break;
case V_028714_SPI_SHADER_SNORM16_ABGR:
args->enabled_channels = 0x5;
args->enabled_channels = 0xf;
packf = ac_build_cvt_pknorm_i16;
break;
case V_028714_SPI_SHADER_UINT16_ABGR:
args->enabled_channels = 0x5;
args->enabled_channels = 0xf;
packi = ac_build_cvt_pk_u16;
if (is_16bit) {
for (unsigned chan = 0; chan < 4; chan++)
@@ -1465,7 +1465,7 @@ si_llvm_init_export_args(struct radv_shader_context *ctx,
break;
case V_028714_SPI_SHADER_SINT16_ABGR:
args->enabled_channels = 0x5;
args->enabled_channels = 0xf;
packi = ac_build_cvt_pk_i16;
if (is_16bit) {
for (unsigned chan = 0; chan < 4; chan++)