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radeonsi/gfx12: fix incorrect condition for when to do clear_buffer via compute

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It was missing the requirement that offset % 4 == 0.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29313>
This commit is contained in:
Marek Olšák
2024-05-21 12:36:17 -04:00
committed by Marge Bot
parent 76b0ad33bc
commit 34be14d957
1 changed files with 3 additions and 5 deletions
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8
src/gallium/drivers/radeonsi/si_compute_blit.c
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@@ -372,11 +372,9 @@ void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
(flags & SI_OP_CS_RENDER_COND_ENABLE ||
/* CP DMA doesn't support large clear value sizes. */
clear_value_size > 4 ||
/* Use compute if CP DMA is non-coherent. */
(sctx->screen->info.cp_sdma_ge_use_system_memory_scope &&
clear_value_size >= 4) ||
/* Use compute if the size is large enough. */
(clear_value_size == 4 && offset % 4 == 0 && size > compute_min_size)))
/* Use compute if the size is large enough. Always prefer compute on GFX12. */
(clear_value_size == 4 && offset % 4 == 0 &&
(size > compute_min_size || sctx->screen->info.cp_sdma_ge_use_system_memory_scope))))
method = SI_COMPUTE_CLEAR_METHOD;
if (method == SI_COMPUTE_CLEAR_METHOD) {