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anv: Enable the new deref-based UBO/SSBO path

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Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
This commit is contained in:
Jason Ekstrand
2018-12-14 18:38:08 -06:00
committed by Jason Ekstrand
parent 63b9aa2e25
commit 34af63fa22
2 changed files with 23 additions and 1 deletions
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20
src/intel/vulkan/anv_nir_apply_pipeline_layout.c
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@@ -184,6 +184,23 @@ lower_res_reindex_intrinsic(nir_intrinsic_instr *intrin,
nir_instr_remove(&intrin->instr); nir_instr_remove(&intrin->instr);
} }
static void
lower_load_vulkan_descriptor(nir_intrinsic_instr *intrin,
struct apply_pipeline_layout_state *state)
{
nir_builder *b = &state->builder;
b->cursor = nir_before_instr(&intrin->instr);
/* We follow the nir_address_format_vk_index_offset model */
assert(intrin->src[0].is_ssa);
nir_ssa_def *vec2 = nir_vec2(b, intrin->src[0].ssa, nir_imm_int(b, 0));
assert(intrin->dest.is_ssa);
nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(vec2));
nir_instr_remove(&intrin->instr);
}
static void static void
lower_image_intrinsic(nir_intrinsic_instr *intrin, lower_image_intrinsic(nir_intrinsic_instr *intrin,
struct apply_pipeline_layout_state *state) struct apply_pipeline_layout_state *state)
@@ -380,6 +397,9 @@ apply_pipeline_layout_block(nir_block *block,
case nir_intrinsic_vulkan_resource_reindex: case nir_intrinsic_vulkan_resource_reindex:
lower_res_reindex_intrinsic(intrin, state); lower_res_reindex_intrinsic(intrin, state);
break; break;
case nir_intrinsic_load_vulkan_descriptor:
lower_load_vulkan_descriptor(intrin, state);
break;
case nir_intrinsic_image_deref_load: case nir_intrinsic_image_deref_load:
case nir_intrinsic_image_deref_store: case nir_intrinsic_image_deref_store:
case nir_intrinsic_image_deref_atomic_add: case nir_intrinsic_image_deref_atomic_add:

4
src/intel/vulkan/anv_pipeline.c
View File

@@ -135,7 +135,6 @@ anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
struct spirv_to_nir_options spirv_options = { struct spirv_to_nir_options spirv_options = {
.lower_workgroup_access_to_offsets = true, .lower_workgroup_access_to_offsets = true,
.lower_ubo_ssbo_access_to_offsets = true,
.caps = { .caps = {
.float64 = device->instance->physicalDevice.info.gen >= 8, .float64 = device->instance->physicalDevice.info.gen >= 8,
.int64 = device->instance->physicalDevice.info.gen >= 8, .int64 = device->instance->physicalDevice.info.gen >= 8,
@@ -214,6 +213,9 @@ anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
NIR_PASS_V(nir, nir_remove_dead_variables, NIR_PASS_V(nir, nir_remove_dead_variables,
nir_var_shader_in | nir_var_shader_out | nir_var_system_value); nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_ubo | nir_var_ssbo,
nir_address_format_vk_index_offset);
if (stage == MESA_SHADER_FRAGMENT) if (stage == MESA_SHADER_FRAGMENT)
NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable); NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable);