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drm-uapi/i915_drm.h: Update from drm-next (2022-04-28)

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git://anongit.freedesktop.org/drm/drm 9bda072a7bec278c424ad660373e69d8e4a3385d

Among other changes, this provides DRM_I915_QUERY_HWCONFIG_BLOB and
DRM_I915_QUERY_GEOMETRY_SUBSLICES, which are needed for DG2 support.

Cc: 22.1 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16174>
This commit is contained in:
Jordan Justen
2022-04-26 13:19:01 -07:00
parent 09e4fd1d84
commit 3477dbd34f
1 changed files with 497 additions and 81 deletions
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578
include/drm-uapi/i915_drm.h
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@@ -172,7 +172,9 @@ enum drm_i915_gem_engine_class {
I915_ENGINE_CLASS_INVALID = -1
};
/*
/**
* struct i915_engine_class_instance - Engine class/instance identifier
*
* There may be more than one engine fulfilling any role within the system.
* Each engine of a class is given a unique instance number and therefore
* any engine can be specified by its class:instance tuplet. APIs that allow
@@ -180,10 +182,21 @@ enum drm_i915_gem_engine_class {
* for this identification.
*/
struct i915_engine_class_instance {
__u16 engine_class; /* see enum drm_i915_gem_engine_class */
__u16 engine_instance;
/**
* @engine_class:
*
* Engine class from enum drm_i915_gem_engine_class
*/
__u16 engine_class;
#define I915_ENGINE_CLASS_INVALID_NONE -1
#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
/**
* @engine_instance:
*
* Engine instance.
*/
__u16 engine_instance;
};
/**
@@ -1118,10 +1131,16 @@ struct drm_i915_gem_exec_object2 {
/**
* When the EXEC_OBJECT_PINNED flag is specified this is populated by
* the user with the GTT offset at which this object will be pinned.
*
* When the I915_EXEC_NO_RELOC flag is specified this must contain the
* presumed_offset of the object.
*
* During execbuffer2 the kernel populates it with the value of the
* current GTT offset of the object, for future presumed_offset writes.
*
* See struct drm_i915_gem_create_ext for the rules when dealing with
* alignment restrictions with I915_MEMORY_CLASS_DEVICE, on devices with
* minimum page sizes, like DG2.
*/
__u64 offset;
@@ -1522,6 +1541,12 @@ struct drm_i915_gem_caching {
#define I915_TILING_NONE 0
#define I915_TILING_X 1
#define I915_TILING_Y 2
/*
* Do not add new tiling types here. The I915_TILING_* values are for
* de-tiling fence registers that no longer exist on modern platforms. Although
* the hardware may support new types of tiling in general (e.g., Tile4), we
* do not need to add them to the uapi that is specific to now-defunct ioctls.
*/
#define I915_TILING_LAST I915_TILING_Y
#define I915_BIT_6_SWIZZLE_NONE 0
@@ -1824,6 +1849,7 @@ struct drm_i915_gem_context_param {
* Extensions:
* i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
* i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
* i915_context_engines_parallel_submit (I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT)
*/
#define I915_CONTEXT_PARAM_ENGINES 0xa
@@ -1846,6 +1872,55 @@ struct drm_i915_gem_context_param {
* attempted to use it, never re-use this context param number.
*/
#define I915_CONTEXT_PARAM_RINGSIZE 0xc
/*
* I915_CONTEXT_PARAM_PROTECTED_CONTENT:
*
* Mark that the context makes use of protected content, which will result
* in the context being invalidated when the protected content session is.
* Given that the protected content session is killed on suspend, the device
* is kept awake for the lifetime of a protected context, so the user should
* make sure to dispose of them once done.
* This flag can only be set at context creation time and, when set to true,
* must be preceded by an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE
* to false. This flag can't be set to true in conjunction with setting the
* I915_CONTEXT_PARAM_BANNABLE flag to false. Creation example:
*
* .. code-block:: C
*
* struct drm_i915_gem_context_create_ext_setparam p_protected = {
* .base = {
* .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
* },
* .param = {
* .param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
* .value = 1,
* }
* };
* struct drm_i915_gem_context_create_ext_setparam p_norecover = {
* .base = {
* .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
* .next_extension = to_user_pointer(&p_protected),
* },
* .param = {
* .param = I915_CONTEXT_PARAM_RECOVERABLE,
* .value = 0,
* }
* };
* struct drm_i915_gem_context_create_ext create = {
* .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
* .extensions = to_user_pointer(&p_norecover);
* };
*
* ctx_id = gem_context_create_ext(drm_fd, &create);
*
* In addition to the normal failure cases, setting this flag during context
* creation can result in the following errors:
*
* -ENODEV: feature not available
* -EPERM: trying to mark a recoverable or not bannable context as protected
*/
#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
/* Must be kept compact -- no holes and well documented */
__u64 value;
@@ -2049,6 +2124,135 @@ struct i915_context_engines_bond {
struct i915_engine_class_instance engines[N__]; \
} __attribute__((packed)) name__
/**
* struct i915_context_engines_parallel_submit - Configure engine for
* parallel submission.
*
* Setup a slot in the context engine map to allow multiple BBs to be submitted
* in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU
* in parallel. Multiple hardware contexts are created internally in the i915 to
* run these BBs. Once a slot is configured for N BBs only N BBs can be
* submitted in each execbuf IOCTL and this is implicit behavior e.g. The user
* doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how
* many BBs there are based on the slot's configuration. The N BBs are the last
* N buffer objects or first N if I915_EXEC_BATCH_FIRST is set.
*
* The default placement behavior is to create implicit bonds between each
* context if each context maps to more than 1 physical engine (e.g. context is
* a virtual engine). Also we only allow contexts of same engine class and these
* contexts must be in logically contiguous order. Examples of the placement
* behavior are described below. Lastly, the default is to not allow BBs to be
* preempted mid-batch. Rather insert coordinated preemption points on all
* hardware contexts between each set of BBs. Flags could be added in the future
* to change both of these default behaviors.
*
* Returns -EINVAL if hardware context placement configuration is invalid or if
* the placement configuration isn't supported on the platform / submission
* interface.
* Returns -ENODEV if extension isn't supported on the platform / submission
* interface.
*
* .. code-block:: none
*
* Examples syntax:
* CS[X] = generic engine of same class, logical instance X
* INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
*
* Example 1 pseudo code:
* set_engines(INVALID)
* set_parallel(engine_index=0, width=2, num_siblings=1,
* engines=CS[0],CS[1])
*
* Results in the following valid placement:
* CS[0], CS[1]
*
* Example 2 pseudo code:
* set_engines(INVALID)
* set_parallel(engine_index=0, width=2, num_siblings=2,
* engines=CS[0],CS[2],CS[1],CS[3])
*
* Results in the following valid placements:
* CS[0], CS[1]
* CS[2], CS[3]
*
* This can be thought of as two virtual engines, each containing two
* engines thereby making a 2D array. However, there are bonds tying the
* entries together and placing restrictions on how they can be scheduled.
* Specifically, the scheduler can choose only vertical columns from the 2D
* array. That is, CS[0] is bonded to CS[1] and CS[2] to CS[3]. So if the
* scheduler wants to submit to CS[0], it must also choose CS[1] and vice
* versa. Same for CS[2] requires also using CS[3].
* VE[0] = CS[0], CS[2]
* VE[1] = CS[1], CS[3]
*
* Example 3 pseudo code:
* set_engines(INVALID)
* set_parallel(engine_index=0, width=2, num_siblings=2,
* engines=CS[0],CS[1],CS[1],CS[3])
*
* Results in the following valid and invalid placements:
* CS[0], CS[1]
* CS[1], CS[3] - Not logically contiguous, return -EINVAL
*/
struct i915_context_engines_parallel_submit {
/**
* @base: base user extension.
*/
struct i915_user_extension base;
/**
* @engine_index: slot for parallel engine
*/
__u16 engine_index;
/**
* @width: number of contexts per parallel engine or in other words the
* number of batches in each submission
*/
__u16 width;
/**
* @num_siblings: number of siblings per context or in other words the
* number of possible placements for each submission
*/
__u16 num_siblings;
/**
* @mbz16: reserved for future use; must be zero
*/
__u16 mbz16;
/**
* @flags: all undefined flags must be zero, currently not defined flags
*/
__u64 flags;
/**
* @mbz64: reserved for future use; must be zero
*/
__u64 mbz64[3];
/**
* @engines: 2-d array of engine instances to configure parallel engine
*
* length = width (i) * num_siblings (j)
* index = j + i * num_siblings
*/
struct i915_engine_class_instance engines[0];
} __attribute__((packed));
#define I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT(name__, N__) struct { \
struct i915_user_extension base; \
__u16 engine_index; \
__u16 width; \
__u16 num_siblings; \
__u16 mbz16; \
__u64 flags; \
__u64 mbz64[3]; \
struct i915_engine_class_instance engines[N__]; \
} __attribute__((packed)) name__
/**
* DOC: Context Engine Map uAPI
*
@@ -2108,6 +2312,7 @@ struct i915_context_param_engines {
__u64 extensions; /* linked chain of extension blocks, 0 terminates */
#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
#define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
struct i915_engine_class_instance engines[0];
} __attribute__((packed));
@@ -2465,24 +2670,65 @@ enum drm_i915_perf_record_type {
DRM_I915_PERF_RECORD_MAX /* non-ABI */
};
/*
/**
* struct drm_i915_perf_oa_config
*
* Structure to upload perf dynamic configuration into the kernel.
*/
struct drm_i915_perf_oa_config {
/** String formatted like "%08x-%04x-%04x-%04x-%012x" */
/**
* @uuid:
*
* String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x"
*/
char uuid[36];
/**
* @n_mux_regs:
*
* Number of mux regs in &mux_regs_ptr.
*/
__u32 n_mux_regs;
/**
* @n_boolean_regs:
*
* Number of boolean regs in &boolean_regs_ptr.
*/
__u32 n_boolean_regs;
/**
* @n_flex_regs:
*
* Number of flex regs in &flex_regs_ptr.
*/
__u32 n_flex_regs;
/*
* These fields are pointers to tuples of u32 values (register address,
* value). For example the expected length of the buffer pointed by
* mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
/**
* @mux_regs_ptr:
*
* Pointer to tuples of u32 values (register address, value) for mux
* registers. Expected length of buffer is (2 * sizeof(u32) *
* &n_mux_regs).
*/
__u64 mux_regs_ptr;
/**
* @boolean_regs_ptr:
*
* Pointer to tuples of u32 values (register address, value) for mux
* registers. Expected length of buffer is (2 * sizeof(u32) *
* &n_boolean_regs).
*/
__u64 boolean_regs_ptr;
/**
* @flex_regs_ptr:
*
* Pointer to tuples of u32 values (register address, value) for mux
* registers. Expected length of buffer is (2 * sizeof(u32) *
* &n_flex_regs).
*/
__u64 flex_regs_ptr;
};
@@ -2493,12 +2739,24 @@ struct drm_i915_perf_oa_config {
* @data_ptr is also depends on the specific @query_id.
*/
struct drm_i915_query_item {
/** @query_id: The id for this query */
/**
* @query_id:
*
* The id for this query. Currently accepted query IDs are:
* - %DRM_I915_QUERY_TOPOLOGY_INFO (see struct drm_i915_query_topology_info)
* - %DRM_I915_QUERY_ENGINE_INFO (see struct drm_i915_engine_info)
* - %DRM_I915_QUERY_PERF_CONFIG (see struct drm_i915_query_perf_config)
* - %DRM_I915_QUERY_MEMORY_REGIONS (see struct drm_i915_query_memory_regions)
* - %DRM_I915_QUERY_HWCONFIG_BLOB (see `GuC HWCONFIG blob uAPI`)
* - %DRM_I915_QUERY_GEOMETRY_SUBSLICES (see struct drm_i915_query_topology_info)
*/
__u64 query_id;
#define DRM_I915_QUERY_TOPOLOGY_INFO 1
#define DRM_I915_QUERY_ENGINE_INFO 2
#define DRM_I915_QUERY_PERF_CONFIG 3
#define DRM_I915_QUERY_MEMORY_REGIONS 4
#define DRM_I915_QUERY_TOPOLOGY_INFO 1
#define DRM_I915_QUERY_ENGINE_INFO 2
#define DRM_I915_QUERY_PERF_CONFIG 3
#define DRM_I915_QUERY_MEMORY_REGIONS 4
#define DRM_I915_QUERY_HWCONFIG_BLOB 5
#define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6
/* Must be kept compact -- no holes and well documented */
/**
@@ -2514,14 +2772,17 @@ struct drm_i915_query_item {
/**
* @flags:
*
* When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
* When &query_id == %DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
*
* When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
* When &query_id == %DRM_I915_QUERY_PERF_CONFIG, must be one of the
* following:
*
* - DRM_I915_QUERY_PERF_CONFIG_LIST
* - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
* - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
* - %DRM_I915_QUERY_PERF_CONFIG_LIST
* - %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
* - %DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
*
* When &query_id == %DRM_I915_QUERY_GEOMETRY_SUBSLICES must contain
* a struct i915_engine_class_instance that references a render engine.
*/
__u32 flags;
#define DRM_I915_QUERY_PERF_CONFIG_LIST 1
@@ -2579,66 +2840,112 @@ struct drm_i915_query {
__u64 items_ptr;
};
/*
* Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
/**
* struct drm_i915_query_topology_info
*
* data: contains the 3 pieces of information :
*
* - the slice mask with one bit per slice telling whether a slice is
* available. The availability of slice X can be queried with the following
* formula :
*
* (data[X / 8] >> (X % 8)) & 1
*
* - the subslice mask for each slice with one bit per subslice telling
* whether a subslice is available. Gen12 has dual-subslices, which are
* similar to two gen11 subslices. For gen12, this array represents dual-
* subslices. The availability of subslice Y in slice X can be queried
* with the following formula :
*
* (data[subslice_offset +
* X * subslice_stride +
* Y / 8] >> (Y % 8)) & 1
*
* - the EU mask for each subslice in each slice with one bit per EU telling
* whether an EU is available. The availability of EU Z in subslice Y in
* slice X can be queried with the following formula :
*
* (data[eu_offset +
* (X * max_subslices + Y) * eu_stride +
* Z / 8] >> (Z % 8)) & 1
* Describes slice/subslice/EU information queried by
* %DRM_I915_QUERY_TOPOLOGY_INFO
*/
struct drm_i915_query_topology_info {
/*
/**
* @flags:
*
* Unused for now. Must be cleared to zero.
*/
__u16 flags;
/**
* @max_slices:
*
* The number of bits used to express the slice mask.
*/
__u16 max_slices;
/**
* @max_subslices:
*
* The number of bits used to express the subslice mask.
*/
__u16 max_subslices;
/**
* @max_eus_per_subslice:
*
* The number of bits in the EU mask that correspond to a single
* subslice's EUs.
*/
__u16 max_eus_per_subslice;
/*
/**
* @subslice_offset:
*
* Offset in data[] at which the subslice masks are stored.
*/
__u16 subslice_offset;
/*
/**
* @subslice_stride:
*
* Stride at which each of the subslice masks for each slice are
* stored.
*/
__u16 subslice_stride;
/*
/**
* @eu_offset:
*
* Offset in data[] at which the EU masks are stored.
*/
__u16 eu_offset;
/*
/**
* @eu_stride:
*
* Stride at which each of the EU masks for each subslice are stored.
*/
__u16 eu_stride;
/**
* @data:
*
* Contains 3 pieces of information :
*
* - The slice mask with one bit per slice telling whether a slice is
* available. The availability of slice X can be queried with the
* following formula :
*
* .. code:: c
*
* (data[X / 8] >> (X % 8)) & 1
*
* Starting with Xe_HP platforms, Intel hardware no longer has
* traditional slices so i915 will always report a single slice
* (hardcoded slicemask = 0x1) which contains all of the platform's
* subslices. I.e., the mask here does not reflect any of the newer
* hardware concepts such as "gslices" or "cslices" since userspace
* is capable of inferring those from the subslice mask.
*
* - The subslice mask for each slice with one bit per subslice telling
* whether a subslice is available. Starting with Gen12 we use the
* term "subslice" to refer to what the hardware documentation
* describes as a "dual-subslices." The availability of subslice Y
* in slice X can be queried with the following formula :
*
* .. code:: c
*
* (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1
*
* - The EU mask for each subslice in each slice, with one bit per EU
* telling whether an EU is available. The availability of EU Z in
* subslice Y in slice X can be queried with the following formula :
*
* .. code:: c
*
* (data[eu_offset +
* (X * max_subslices + Y) * eu_stride +
* Z / 8
* ] >> (Z % 8)) & 1
*/
__u8 data[];
};
@@ -2726,14 +3033,20 @@ struct drm_i915_engine_info {
/** @flags: Engine flags. */
__u64 flags;
#define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0)
/** @capabilities: Capabilities of this engine. */
__u64 capabilities;
#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
/** @logical_instance: Logical instance of engine */
__u16 logical_instance;
/** @rsvd1: Reserved fields. */
__u64 rsvd1[4];
__u16 rsvd1[3];
/** @rsvd2: Reserved fields. */
__u64 rsvd2[3];
};
/**
@@ -2753,52 +3066,68 @@ struct drm_i915_query_engine_info {
struct drm_i915_engine_info engines[];
};
/*
* Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
/**
* struct drm_i915_query_perf_config
*
* Data written by the kernel with query %DRM_I915_QUERY_PERF_CONFIG and
* %DRM_I915_QUERY_GEOMETRY_SUBSLICES.
*/
struct drm_i915_query_perf_config {
union {
/*
* When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets
* this fields to the number of configurations available.
/**
* @n_configs:
*
* When &drm_i915_query_item.flags ==
* %DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets this fields to
* the number of configurations available.
*/
__u64 n_configs;
/*
* When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
* i915 will use the value in this field as configuration
* identifier to decide what data to write into config_ptr.
/**
* @config:
*
* When &drm_i915_query_item.flags ==
* %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID, i915 will use the
* value in this field as configuration identifier to decide
* what data to write into config_ptr.
*/
__u64 config;
/*
* When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
* i915 will use the value in this field as configuration
* identifier to decide what data to write into config_ptr.
/**
* @uuid:
*
* When &drm_i915_query_item.flags ==
* %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID, i915 will use the
* value in this field as configuration identifier to decide
* what data to write into config_ptr.
*
* String formatted like "%08x-%04x-%04x-%04x-%012x"
*/
char uuid[36];
};
/*
/**
* @flags:
*
* Unused for now. Must be cleared to zero.
*/
__u32 flags;
/*
* When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
* write an array of __u64 of configuration identifiers.
/**
* @data:
*
* When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
* write a struct drm_i915_perf_oa_config. If the following fields of
* drm_i915_perf_oa_config are set not set to 0, i915 will write into
* the associated pointers the values of submitted when the
* When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_LIST,
* i915 will write an array of __u64 of configuration identifiers.
*
* When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_DATA,
* i915 will write a struct drm_i915_perf_oa_config. If the following
* fields of struct drm_i915_perf_oa_config are not set to 0, i915 will
* write into the associated pointers the values of submitted when the
* configuration was created :
*
* - n_mux_regs
* - n_boolean_regs
* - n_flex_regs
* - &drm_i915_perf_oa_config.n_mux_regs
* - &drm_i915_perf_oa_config.n_boolean_regs
* - &drm_i915_perf_oa_config.n_flex_regs
*/
__u8 data[];
};
@@ -2936,6 +3265,16 @@ struct drm_i915_query_memory_regions {
struct drm_i915_memory_region_info regions[];
};
/**
* DOC: GuC HWCONFIG blob uAPI
*
* The GuC produces a blob with information about the current device.
* i915 reads this blob from GuC and makes it available via this uAPI.
*
* The format and meaning of the blob content are documented in the
* Programmer's Reference Manual.
*/
/**
* struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added
* extension support using struct i915_user_extension.
@@ -2952,11 +3291,40 @@ struct drm_i915_gem_create_ext {
*
* The (page-aligned) allocated size for the object will be returned.
*
* Note that for some devices we have might have further minimum
* page-size restrictions(larger than 4K), like for device local-memory.
* However in general the final size here should always reflect any
* rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS
* extension to place the object in device local-memory.
*
* DG2 64K min page size implications:
*
* On discrete platforms, starting from DG2, we have to contend with GTT
* page size restrictions when dealing with I915_MEMORY_CLASS_DEVICE
* objects. Specifically the hardware only supports 64K or larger GTT
* page sizes for such memory. The kernel will already ensure that all
* I915_MEMORY_CLASS_DEVICE memory is allocated using 64K or larger page
* sizes underneath.
*
* Note that the returned size here will always reflect any required
* rounding up done by the kernel, i.e 4K will now become 64K on devices
* such as DG2.
*
* Special DG2 GTT address alignment requirement:
*
* The GTT alignment will also need to be at least 2M for such objects.
*
* Note that due to how the hardware implements 64K GTT page support, we
* have some further complications:
*
* 1) The entire PDE (which covers a 2MB virtual address range), must
* contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same
* PDE is forbidden by the hardware.
*
* 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM
* objects.
*
* To keep things simple for userland, we mandate that any GTT mappings
* must be aligned to and rounded up to 2MB. The kernel will internally
* pad them out to the next 2MB boundary. As this only wastes virtual
* address space and avoids userland having to copy any needlessly
* complicated PDE sharing scheme (coloring) and only affects DG2, this
* is deemed to be a good compromise.
*/
__u64 size;
/**
@@ -2979,8 +3347,12 @@ struct drm_i915_gem_create_ext {
*
* For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see
* struct drm_i915_gem_create_ext_memory_regions.
*
* For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see
* struct drm_i915_gem_create_ext_protected_content.
*/
#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
#define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1
__u64 extensions;
};
@@ -3038,6 +3410,50 @@ struct drm_i915_gem_create_ext_memory_regions {
__u64 regions;
};
/**
* struct drm_i915_gem_create_ext_protected_content - The
* I915_OBJECT_PARAM_PROTECTED_CONTENT extension.
*
* If this extension is provided, buffer contents are expected to be protected
* by PXP encryption and require decryption for scan out and processing. This
* is only possible on platforms that have PXP enabled, on all other scenarios
* using this extension will cause the ioctl to fail and return -ENODEV. The
* flags parameter is reserved for future expansion and must currently be set
* to zero.
*
* The buffer contents are considered invalid after a PXP session teardown.
*
* The encryption is guaranteed to be processed correctly only if the object
* is submitted with a context created using the
* I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. This will also enable extra checks
* at submission time on the validity of the objects involved.
*
* Below is an example on how to create a protected object:
*
* .. code-block:: C
*
* struct drm_i915_gem_create_ext_protected_content protected_ext = {
* .base = { .name = I915_GEM_CREATE_EXT_PROTECTED_CONTENT },
* .flags = 0,
* };
* struct drm_i915_gem_create_ext create_ext = {
* .size = PAGE_SIZE,
* .extensions = (uintptr_t)&protected_ext,
* };
*
* int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
* if (err) ...
*/
struct drm_i915_gem_create_ext_protected_content {
/** @base: Extension link. See struct i915_user_extension. */
struct i915_user_extension base;
/** @flags: reserved for future usage, currently MBZ */
__u32 flags;
};
/* ID of the protected content session managed by i915 when PXP is active */
#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
#if defined(__cplusplus)
}
#endif