panfrost: Fix BI_BLEND packing
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
This commit is contained in:

committed by
Tomeu Vizoso

parent
e34add229f
commit
3439c24bdb
@@ -1014,16 +1014,17 @@ bi_pack_add_atest(bi_clause *clause, bi_instruction *ins, struct bi_registers *r
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}
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}
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static unsigned
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static unsigned
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bi_pack_add_blend(bi_instruction *ins, struct bi_registers *regs)
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bi_pack_add_blend(bi_clause *clause, bi_instruction *ins, struct bi_registers *regs)
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{
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{
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struct bifrost_add_inst pack = {
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struct bifrost_add_inst pack = {
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.src0 = bi_get_src(ins, regs, 0, false),
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.src0 = bi_get_src(ins, regs, 1, false),
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.op = BIFROST_ADD_OP_BLEND
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.op = BIFROST_ADD_OP_BLEND
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};
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};
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/* TODO: Pack location in uniform_const */
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/* TODO: Pack location in uniform_const */
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assert(ins->blend_location == 0);
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assert(ins->blend_location == 0);
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bi_read_data_register(clause, ins);
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RETURN_PACKED(pack);
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RETURN_PACKED(pack);
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}
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}
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@@ -1065,7 +1066,7 @@ bi_pack_add(bi_clause *clause, bi_bundle bundle, struct bi_registers *regs)
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case BI_CMP:
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case BI_CMP:
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return BIFROST_ADD_NOP;
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return BIFROST_ADD_NOP;
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case BI_BLEND:
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case BI_BLEND:
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return bi_pack_add_blend(bundle.add, regs);
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return bi_pack_add_blend(clause, bundle.add, regs);
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case BI_BITWISE:
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case BI_BITWISE:
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case BI_CONVERT:
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case BI_CONVERT:
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case BI_DISCARD:
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case BI_DISCARD:
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@@ -156,6 +156,12 @@ bi_schedule(bi_context *ctx)
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u->data_register_write_barrier = true;
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u->data_register_write_barrier = true;
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}
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}
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if (ins->type == BI_ATEST)
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u->dependencies |= (1 << 6);
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if (ins->type == BI_BLEND)
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u->dependencies |= (1 << 6) | (1 << 7);
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ids = ids & 1;
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ids = ids & 1;
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last_id = u->scoreboard_id;
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last_id = u->scoreboard_id;
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u->back_to_back = false;
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u->back_to_back = false;
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@@ -31,7 +31,7 @@ unsigned bi_class_props[BI_NUM_CLASSES] = {
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[BI_ATEST] = BI_SCHED_HI_LATENCY | BI_SCHED_ADD,
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[BI_ATEST] = BI_SCHED_HI_LATENCY | BI_SCHED_ADD,
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[BI_BRANCH] = BI_SCHED_HI_LATENCY | BI_SCHED_ADD,
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[BI_BRANCH] = BI_SCHED_HI_LATENCY | BI_SCHED_ADD,
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[BI_CMP] = BI_GENERIC | BI_MODS | BI_SCHED_ALL,
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[BI_CMP] = BI_GENERIC | BI_MODS | BI_SCHED_ALL,
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[BI_BLEND] = BI_SCHED_HI_LATENCY | BI_SCHED_ADD | BI_VECTOR,
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[BI_BLEND] = BI_SCHED_HI_LATENCY | BI_SCHED_ADD | BI_VECTOR | BI_DATA_REG_SRC,
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[BI_BITWISE] = BI_GENERIC | BI_SCHED_ALL,
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[BI_BITWISE] = BI_GENERIC | BI_SCHED_ALL,
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[BI_COMBINE] = 0,
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[BI_COMBINE] = 0,
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[BI_CONVERT] = BI_SCHED_ALL | BI_SWIZZLABLE,
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[BI_CONVERT] = BI_SCHED_ALL | BI_SWIZZLABLE,
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@@ -147,16 +147,16 @@ bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
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.type = BI_BLEND,
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.type = BI_BLEND,
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.blend_location = nir_intrinsic_base(instr),
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.blend_location = nir_intrinsic_base(instr),
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.src = {
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.src = {
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bir_src_index(&instr->src[0]),
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BIR_INDEX_REGISTER | 60 /* Can this be arbitrary? */,
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BIR_INDEX_REGISTER | 60 /* Can this be arbitrary? */,
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bir_src_index(&instr->src[0])
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},
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},
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.src_types = {
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.src_types = {
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nir_type_uint32,
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nir_type_float32,
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nir_type_float32,
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nir_type_uint32
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},
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},
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.swizzle = {
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.swizzle = {
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{ 0 },
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{ 0, 1, 2, 3 },
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{ 0, 1, 2, 3 }
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{ 0 }
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},
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},
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.dest = BIR_INDEX_REGISTER | 48 /* Looks like magic */,
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.dest = BIR_INDEX_REGISTER | 48 /* Looks like magic */,
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.dest_type = nir_type_uint32,
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.dest_type = nir_type_uint32,
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