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intel: simplify is_haswell checks, part 1

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Generated with:

files=`git grep is_haswell | cut -d: -f1 | sort | uniq`
for file in $files; do
        cat $file | \
                sed "s/devinfo->ver <= 7 && !devinfo->is_haswell/devinfo->verx10 <= 70/g" | \
                sed "s/devinfo->ver >= 8 || devinfo->is_haswell/devinfo->verx10 >= 75/g" | \
                sed "s/devinfo->is_haswell || devinfo->ver >= 8/devinfo->verx10 >= 75/g" | \
                sed "s/devinfo.is_haswell || devinfo.ver >= 8/devinfo.verx10 >= 75/g" | \
                sed "s/devinfo->ver > 7 || devinfo->is_haswell/devinfo->verx10 >= 75/g" | \
                sed "s/devinfo->ver == 7 && !devinfo->is_haswell/devinfo->verx10 == 70/g" | \
                sed "s/devinfo.ver == 7 && !devinfo.is_haswell/devinfo.verx10 == 70/g" | \
                sed "s/devinfo->ver < 8 && !devinfo->is_haswell/devinfo->verx10 <= 70/g" | \
                sed "s/device->info.ver == 7 && !device->info.is_haswell/device->info.verx10 == 70/g" \
                > tmpXXX
        mv tmpXXX $file
done

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10810>
This commit is contained in:
Marcin Ślusarz
2021-05-14 18:04:46 +02:00
committed by Marge Bot
parent 3a29e45a90
commit 3340d5ee02
33 changed files with 97 additions and 97 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/intel/blorp/blorp_blit.c
View File

@@ -2074,7 +2074,7 @@ try_blorp_blit(struct blorp_batch *batch,
params->dst.view.format = ISL_FORMAT_R32_UINT;
}
if (devinfo->ver <= 7 && !devinfo->is_haswell &&
if (devinfo->verx10 <= 70 &&
!isl_swizzle_is_identity(params->src.view.swizzle)) {
wm_prog_key->src_swizzle = params->src.view.swizzle;
params->src.view.swizzle = ISL_SWIZZLE_IDENTITY;

18
src/intel/compiler/brw_eu.h
View File

@@ -623,7 +623,7 @@ brw_dp_untyped_atomic_desc(const struct intel_device_info *devinfo,
assert(exec_size <= 8 || exec_size == 16);
unsigned msg_type;
if (devinfo->ver >= 8 || devinfo->is_haswell) {
if (devinfo->verx10 >= 75) {
if (exec_size > 0) {
msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP;
} else {
@@ -678,14 +678,14 @@ brw_dp_untyped_surface_rw_desc(const struct intel_device_info *devinfo,
unsigned msg_type;
if (write) {
if (devinfo->ver >= 8 || devinfo->is_haswell) {
if (devinfo->verx10 >= 75) {
msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE;
} else {
msg_type = GFX7_DATAPORT_DC_UNTYPED_SURFACE_WRITE;
}
} else {
/* Read */
if (devinfo->ver >= 8 || devinfo->is_haswell) {
if (devinfo->verx10 >= 75) {
msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ;
} else {
msg_type = GFX7_DATAPORT_DC_UNTYPED_SURFACE_READ;
@@ -693,7 +693,7 @@ brw_dp_untyped_surface_rw_desc(const struct intel_device_info *devinfo,
}
/* SIMD4x2 is only valid for read messages on IVB; use SIMD8 instead */
if (write && devinfo->ver == 7 && !devinfo->is_haswell && exec_size == 0)
if (write && devinfo->verx10 == 70 && exec_size == 0)
exec_size = 8;
/* See also MDC_SM3 in the SKL PRM Vol 2d. */
@@ -730,7 +730,7 @@ brw_dp_byte_scattered_rw_desc(const struct intel_device_info *devinfo,
{
assert(exec_size <= 8 || exec_size == 16);
assert(devinfo->ver > 7 || devinfo->is_haswell);
assert(devinfo->verx10 >= 75);
const unsigned msg_type =
write ? HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE :
HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ;
@@ -940,7 +940,7 @@ brw_dp_typed_atomic_desc(const struct intel_device_info *devinfo,
assert(exec_group % 8 == 0);
unsigned msg_type;
if (devinfo->ver >= 8 || devinfo->is_haswell) {
if (devinfo->verx10 >= 75) {
if (exec_size == 0) {
msg_type = HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2;
} else {
@@ -977,13 +977,13 @@ brw_dp_typed_surface_rw_desc(const struct intel_device_info *devinfo,
unsigned msg_type;
if (write) {
if (devinfo->ver >= 8 || devinfo->is_haswell) {
if (devinfo->verx10 >= 75) {
msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE;
} else {
msg_type = GFX7_DATAPORT_RC_TYPED_SURFACE_WRITE;
}
} else {
if (devinfo->ver >= 8 || devinfo->is_haswell) {
if (devinfo->verx10 >= 75) {
msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ;
} else {
msg_type = GFX7_DATAPORT_RC_TYPED_SURFACE_READ;
@@ -992,7 +992,7 @@ brw_dp_typed_surface_rw_desc(const struct intel_device_info *devinfo,
/* See also MDC_SG3 in the SKL PRM Vol 2d. */
unsigned msg_control;
if (devinfo->ver >= 8 || devinfo->is_haswell) {
if (devinfo->verx10 >= 75) {
/* See also MDC_SG3 in the SKL PRM Vol 2d. */
const unsigned slot_group = exec_size == 0 ? 0 : /* SIMD4x2 */
1 + ((exec_group / 8) % 2);

22
src/intel/compiler/brw_eu_emit.c
View File

@@ -321,7 +321,7 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
* descriptions for registers in align_16 as align_1:
*/
brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4);
} else if (devinfo->ver == 7 && !devinfo->is_haswell &&
} else if (devinfo->verx10 == 70 &&
reg.type == BRW_REGISTER_TYPE_DF &&
reg.vstride == BRW_VERTICAL_STRIDE_2) {
/* From SNB PRM:
@@ -428,7 +428,7 @@ brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
* descriptions for registers in align_16 as align_1:
*/
brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4);
} else if (devinfo->ver == 7 && !devinfo->is_haswell &&
} else if (devinfo->verx10 == 70 &&
reg.type == BRW_REGISTER_TYPE_DF &&
reg.vstride == BRW_VERTICAL_STRIDE_2) {
/* From SNB PRM:
@@ -1108,7 +1108,7 @@ brw_MOV(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0)
* To avoid the problems that causes, we use an <X,2,0> source region to
* read each element twice.
*/
if (devinfo->ver == 7 && !devinfo->is_haswell &&
if (devinfo->verx10 == 70 &&
brw_get_default_access_mode(p) == BRW_ALIGN_1 &&
dest.type == BRW_REGISTER_TYPE_DF &&
(src0.type == BRW_REGISTER_TYPE_F ||
@@ -2573,7 +2573,7 @@ void brw_adjust_sampler_state_pointer(struct brw_codegen *p,
uint32_t sampler = sampler_index.ud;
if (sampler >= 16) {
assert(devinfo->is_haswell || devinfo->ver >= 8);
assert(devinfo->verx10 >= 75);
brw_ADD(p,
get_element_ud(header, 3),
get_element_ud(brw_vec8_grf(0, 0), 3),
@@ -2581,7 +2581,7 @@ void brw_adjust_sampler_state_pointer(struct brw_codegen *p,
}
} else {
/* Non-const sampler array indexing case */
if (devinfo->ver < 8 && !devinfo->is_haswell) {
if (devinfo->verx10 <= 70) {
return;
}
@@ -3108,12 +3108,12 @@ brw_untyped_atomic(struct brw_codegen *p,
bool header_present)
{
const struct intel_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
const unsigned sfid = (devinfo->verx10 >= 75 ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GFX7_SFID_DATAPORT_DATA_CACHE);
const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1;
/* SIMD4x2 untyped atomic instructions only exist on HSW+ */
const bool has_simd4x2 = devinfo->ver >= 8 || devinfo->is_haswell;
const bool has_simd4x2 = devinfo->verx10 >= 75;
const unsigned exec_size = align1 ? 1 << brw_get_default_exec_size(p) :
has_simd4x2 ? 0 : 8;
const unsigned response_length =
@@ -3143,7 +3143,7 @@ brw_untyped_surface_read(struct brw_codegen *p,
unsigned num_channels)
{
const struct intel_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
const unsigned sfid = (devinfo->verx10 >= 75 ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GFX7_SFID_DATAPORT_DATA_CACHE);
const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1;
@@ -3166,12 +3166,12 @@ brw_untyped_surface_write(struct brw_codegen *p,
bool header_present)
{
const struct intel_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
const unsigned sfid = (devinfo->verx10 >= 75 ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GFX7_SFID_DATAPORT_DATA_CACHE);
const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1;
/* SIMD4x2 untyped surface write instructions only exist on HSW+ */
const bool has_simd4x2 = devinfo->ver >= 8 || devinfo->is_haswell;
const bool has_simd4x2 = devinfo->verx10 >= 75;
const unsigned exec_size = align1 ? 1 << brw_get_default_exec_size(p) :
has_simd4x2 ? 0 : 8;
const unsigned desc =
@@ -3551,7 +3551,7 @@ void brw_shader_time_add(struct brw_codegen *p,
uint32_t surf_index)
{
const struct intel_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
const unsigned sfid = (devinfo->verx10 >= 75 ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GFX7_SFID_DATAPORT_DATA_CACHE);
assert(devinfo->ver >= 7);

10
src/intel/compiler/brw_eu_validate.c
View File

@@ -762,7 +762,7 @@ general_restrictions_based_on_operand_types(const struct intel_device_info *devi
* 32-bit elements, so they are doubled. For evaluating the validity of an
* instruction, we halve them.
*/
if (devinfo->ver == 7 && !devinfo->is_haswell &&
if (devinfo->verx10 == 70 &&
exec_type_size == 8 && dst_type_size == 4)
dst_type_size = 8;
@@ -946,7 +946,7 @@ general_restrictions_on_region_parameters(const struct intel_device_info *devinf
"Destination Horizontal Stride must be 1");
if (num_sources >= 1) {
if (devinfo->is_haswell || devinfo->ver >= 8) {
if (devinfo->verx10 >= 75) {
ERROR_IF(brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE &&
brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 &&
brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_2 &&
@@ -961,7 +961,7 @@ general_restrictions_on_region_parameters(const struct intel_device_info *devinf
}
if (num_sources == 2) {
if (devinfo->is_haswell || devinfo->ver >= 8) {
if (devinfo->verx10 >= 75) {
ERROR_IF(brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE &&
brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 &&
brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_2 &&
@@ -1005,7 +1005,7 @@ general_restrictions_on_region_parameters(const struct intel_device_info *devinf
* 32-bit elements, so they are doubled. For evaluating the validity of an
* instruction, we halve them.
*/
if (devinfo->ver == 7 && !devinfo->is_haswell &&
if (devinfo->verx10 == 70 &&
element_size == 8)
element_size = 4;
@@ -1447,7 +1447,7 @@ region_alignment_rules(const struct intel_device_info *devinfo,
* 32-bit elements, so they are doubled. For evaluating the validity of an
* instruction, we halve them.
*/
if (devinfo->ver == 7 && !devinfo->is_haswell &&
if (devinfo->verx10 == 70 &&
element_size == 8)
element_size = 4;

22
src/intel/compiler/brw_fs.cpp
View File

@@ -4228,7 +4228,7 @@ fs_visitor::lower_mulh_inst(fs_inst *inst, bblock_t *block)
if (mul->src[1].file == IMM) {
mul->src[1] = brw_imm_uw(mul->src[1].ud);
}
} else if (devinfo->ver == 7 && !devinfo->is_haswell &&
} else if (devinfo->verx10 == 70 &&
inst->group > 0) {
/* Among other things the quarter control bits influence which
* accumulator register is used by the hardware for instructions
@@ -4555,7 +4555,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
assert(length == 0);
length = 2;
} else if ((devinfo->ver <= 7 && !devinfo->is_haswell &&
} else if ((devinfo->verx10 <= 70 &&
prog_data->uses_kill) ||
(devinfo->ver < 11 &&
(color1.file != BAD_FILE || key->nr_color_regions > 1))) {
@@ -5013,7 +5013,7 @@ lower_sampler_logical_send_gfx5(const fs_builder &bld, fs_inst *inst, opcode op,
static bool
is_high_sampler(const struct intel_device_info *devinfo, const fs_reg &sampler)
{
if (devinfo->ver < 8 && !devinfo->is_haswell)
if (devinfo->verx10 <= 70)
return false;
return sampler.file != IMM || sampler.ud >= 16;
@@ -5041,7 +5041,7 @@ sampler_msg_type(const intel_device_info *devinfo,
case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
return GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
case SHADER_OPCODE_TXD:
assert(!shadow_compare || devinfo->ver >= 8 || devinfo->is_haswell);
assert(!shadow_compare || devinfo->verx10 >= 75);
return shadow_compare ? HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE :
GFX5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
case SHADER_OPCODE_TXF:
@@ -5720,7 +5720,7 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst)
/* Untyped Surface messages go through the data cache but the SFID value
* changed on Haswell.
*/
sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
sfid = (devinfo->verx10 >= 75 ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GFX7_SFID_DATAPORT_DATA_CACHE);
break;
@@ -5731,7 +5731,7 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst)
/* Typed surface messages go through the render cache on IVB and the
* data cache on HSW+.
*/
sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
sfid = (devinfo->verx10 >= 75 ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GFX6_SFID_DATAPORT_RENDER_CACHE);
break;
@@ -6121,7 +6121,7 @@ lower_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst)
GFX5_SAMPLER_MESSAGE_SAMPLE_LD,
simd_mode, 0);
} else if (alignment >= 4) {
inst->sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
inst->sfid = (devinfo->verx10 >= 75 ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GFX7_SFID_DATAPORT_DATA_CACHE);
inst->desc |= brw_dp_untyped_surface_rw_desc(devinfo, inst->exec_size,
@@ -6684,7 +6684,7 @@ get_fpu_lowered_simd_width(const struct intel_device_info *devinfo,
* the compressed instruction which will be just wrong under
* non-uniform control flow.
*/
if (devinfo->ver == 7 && !devinfo->is_haswell &&
if (devinfo->verx10 == 70 &&
(exec_type_size == 8 || type_sz(inst->dst.type) == 8))
max_width = MIN2(max_width, 4);
}
@@ -6854,7 +6854,7 @@ get_lowered_simd_width(const struct intel_device_info *devinfo,
* coissuing would affect CMP instructions not otherwise affected by
* the errata.
*/
const unsigned max_width = (devinfo->ver == 7 && !devinfo->is_haswell &&
const unsigned max_width = (devinfo->verx10 == 70 &&
!inst->dst.is_null() ? 8 : ~0);
return MIN2(max_width, get_fpu_lowered_simd_width(devinfo, inst));
}
@@ -6955,7 +6955,7 @@ get_lowered_simd_width(const struct intel_device_info *devinfo,
* numbers don't appear to work on Sandybridge either.
*/
return (devinfo->ver == 4 || devinfo->ver == 6 ||
(devinfo->ver == 7 && !devinfo->is_haswell) ?
(devinfo->verx10 == 70) ?
MIN2(8, inst->exec_size) : MIN2(16, inst->exec_size));
case SHADER_OPCODE_MULH:
@@ -9474,7 +9474,7 @@ cs_fill_push_const_info(const struct intel_device_info *devinfo,
{
const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
int subgroup_id_index = get_subgroup_id_param_index(devinfo, prog_data);
bool cross_thread_supported = devinfo->ver > 7 || devinfo->is_haswell;
bool cross_thread_supported = devinfo->verx10 >= 75;
/* The thread ID should be stored in the last param dword */
assert(subgroup_id_index == -1 ||

18
src/intel/compiler/brw_fs_generator.cpp
View File

@@ -104,7 +104,7 @@ brw_reg_from_fs_reg(const struct intel_device_info *devinfo, fs_inst *inst,
brw_reg = stride(brw_reg, width * reg->stride, width, reg->stride);
}
if (devinfo->ver == 7 && !devinfo->is_haswell) {
if (devinfo->verx10 == 70) {
/* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
* "Each DF (Double Float) operand uses an element size of 4 rather
* than 8 and all regioning parameters are twice what the values
@@ -171,7 +171,7 @@ brw_reg_from_fs_reg(const struct intel_device_info *devinfo, fs_inst *inst,
* region, but on IVB and BYT DF regions must be programmed in terms of
* floats. A <0,2,1> region accomplishes this.
*/
if (devinfo->ver == 7 && !devinfo->is_haswell &&
if (devinfo->verx10 == 70 &&
type_sz(reg->type) == 8 &&
brw_reg.vstride == BRW_VERTICAL_STRIDE_0 &&
brw_reg.width == BRW_WIDTH_1 &&
@@ -397,7 +397,7 @@ fs_generator::fire_fb_write(fs_inst *inst,
void
fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
{
if (devinfo->ver < 8 && !devinfo->is_haswell) {
if (devinfo->verx10 <= 70) {
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_default_flag_reg(p, 0, 0);
}
@@ -549,7 +549,7 @@ fs_generator::generate_mov_indirect(fs_inst *inst,
brw_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl);
if (type_sz(reg.type) > 4 &&
((devinfo->ver == 7 && !devinfo->is_haswell) ||
((devinfo->verx10 == 70) ||
devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) ||
!devinfo->has_64bit_float || devinfo->verx10 >= 125)) {
/* IVB has an issue (which we found empirically) where it reads two
@@ -606,7 +606,7 @@ fs_generator::generate_shuffle(fs_inst *inst,
/* Ivy bridge has some strange behavior that makes this a real pain to
* implement for 64-bit values so we just don't bother.
*/
assert(devinfo->ver >= 8 || devinfo->is_haswell || type_sz(src.type) <= 4);
assert(devinfo->verx10 >= 75 || type_sz(src.type) <= 4);
/* Because we're using the address register, we're limited to 8-wide
* execution on gfx7. On gfx8, we're limited to 16-wide by the address
@@ -714,7 +714,7 @@ fs_generator::generate_shuffle(fs_inst *inst,
brw_ADD(p, addr, addr, brw_imm_uw(src_start_offset));
if (type_sz(src.type) > 4 &&
((devinfo->ver == 7 && !devinfo->is_haswell) ||
((devinfo->verx10 == 70) ||
devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) ||
!devinfo->has_64bit_float)) {
/* IVB has an issue (which we found empirically) where it reads
@@ -2019,7 +2019,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
brw_set_default_swsb(p, inst->sched);
unsigned exec_size = inst->exec_size;
if (devinfo->ver == 7 && !devinfo->is_haswell &&
if (devinfo->verx10 == 70 &&
(get_exec_type_size(inst) == 8 || type_sz(inst->dst.type) == 8)) {
exec_size *= 2;
}
@@ -2123,7 +2123,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
brw_F16TO32(p, dst, src[0]);
break;
case BRW_OPCODE_CMP:
if (inst->exec_size >= 16 && devinfo->ver == 7 && !devinfo->is_haswell &&
if (inst->exec_size >= 16 && devinfo->verx10 == 70 &&
dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
/* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
* implemented in the compiler is not sufficient. Overriding the
@@ -2135,7 +2135,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
break;
case BRW_OPCODE_CMPN:
if (inst->exec_size >= 16 && devinfo->ver == 7 && !devinfo->is_haswell &&
if (inst->exec_size >= 16 && devinfo->verx10 == 70 &&
dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
/* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
* implemented in the compiler is not sufficient. Overriding the

2
src/intel/compiler/brw_fs_lower_regioning.cpp
View File

@@ -201,7 +201,7 @@ namespace {
case SHADER_OPCODE_BROADCAST:
case SHADER_OPCODE_MOV_INDIRECT:
return (((devinfo->ver == 7 && !devinfo->is_haswell) ||
return (((devinfo->verx10 == 70) ||
devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) ||
devinfo->verx10 >= 125) && type_sz(inst->src[0].type) > 4) ||
(devinfo->verx10 >= 125 &&

2
src/intel/compiler/brw_fs_nir.cpp
View File

@@ -4338,7 +4338,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
* to flush it too.
*/
const bool needs_render_fence =
devinfo->ver == 7 && !devinfo->is_haswell;
devinfo->verx10 == 70;
/* Be conservative in Gfx11+ and always stall in a fence. Since there
* are two different fences, and shader might want to synchronize

2
src/intel/compiler/brw_ir_performance.cpp
View File

@@ -1054,7 +1054,7 @@ namespace {
}
case GFX7_SFID_DATAPORT_DATA_CACHE:
case HSW_SFID_DATAPORT_DATA_CACHE_1:
if (devinfo->ver >= 8 || devinfo->is_haswell) {
if (devinfo->verx10 >= 75) {
switch (brw_dp_desc_msg_type(devinfo, info.desc)) {
case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP:
case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2:

4
src/intel/compiler/brw_nir.c
View File

@@ -548,7 +548,7 @@ brw_nir_no_indirect_mask(const struct brw_compiler *compiler,
* indirects as scratch all the time, we may easily exceed this limit
* without having any fallback.
*/
if (is_scalar && devinfo->ver <= 7 && !devinfo->is_haswell)
if (is_scalar && devinfo->verx10 <= 70)
indirect_mask |= nir_var_function_temp;
return indirect_mask;
@@ -1265,7 +1265,7 @@ brw_nir_apply_sampler_key(nir_shader *nir,
}
/* Prior to Haswell, we have to lower gradients on shadow samplers */
tex_options.lower_txd_shadow = devinfo->ver < 8 && !devinfo->is_haswell;
tex_options.lower_txd_shadow = devinfo->verx10 <= 70;
tex_options.lower_y_uv_external = key_tex->y_uv_image_mask;
tex_options.lower_y_u_v_external = key_tex->y_u_v_image_mask;

2
src/intel/compiler/brw_nir_analyze_ubo_ranges.c
View File

@@ -202,7 +202,7 @@ brw_nir_analyze_ubo_ranges(const struct brw_compiler *compiler,
{
const struct intel_device_info *devinfo = compiler->devinfo;
if ((devinfo->ver <= 7 && !devinfo->is_haswell) ||
if ((devinfo->verx10 <= 70) ||
!compiler->scalar_stage[nir->info.stage]) {
memset(out_ranges, 0, 4 * sizeof(struct brw_ubo_range));
return;

8
src/intel/compiler/brw_nir_lower_image_load_store.c
View File

@@ -299,7 +299,7 @@ convert_color_for_load(nir_builder *b, const struct intel_device_info *devinfo,
* their least significant bits. However, the data in the high bits is
* garbage so we have to discard it.
*/
if (devinfo->ver == 7 && !devinfo->is_haswell &&
if (devinfo->verx10 == 70 &&
(lower_fmt == ISL_FORMAT_R16_UINT ||
lower_fmt == ISL_FORMAT_R8_UINT))
color = nir_format_mask_uvec(b, color, lower.bits);
@@ -408,7 +408,7 @@ lower_image_load_instr(nir_builder *b,
nir_ssa_def *coord = intrin->src[1].ssa;
nir_ssa_def *do_load = image_coord_is_in_bounds(b, deref, coord);
if (devinfo->ver == 7 && !devinfo->is_haswell) {
if (devinfo->verx10 == 70) {
/* Check whether the first stride component (i.e. the Bpp value)
* is greater than four, what on Gfx7 indicates that a surface of
* type RAW has been bound for untyped access. Reading or writing
@@ -556,7 +556,7 @@ lower_image_store_instr(nir_builder *b,
nir_ssa_def *coord = intrin->src[1].ssa;
nir_ssa_def *do_store = image_coord_is_in_bounds(b, deref, coord);
if (devinfo->ver == 7 && !devinfo->is_haswell) {
if (devinfo->verx10 == 70) {
/* Check whether the first stride component (i.e. the Bpp value)
* is greater than four, what on Gfx7 indicates that a surface of
* type RAW has been bound for untyped access. Reading or writing
@@ -595,7 +595,7 @@ lower_image_atomic_instr(nir_builder *b,
const struct intel_device_info *devinfo,
nir_intrinsic_instr *intrin)
{
if (devinfo->is_haswell || devinfo->ver >= 8)
if (devinfo->verx10 >= 75)
return false;
nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);

2
src/intel/compiler/brw_vec4.cpp
View File

@@ -2227,7 +2227,7 @@ get_lowered_simd_width(const struct intel_device_info *devinfo,
* compressed instruction bug in gfx7, which is another reason to enforce
* this limit).
*/
if (devinfo->ver == 7 && !devinfo->is_haswell &&
if (devinfo->verx10 == 70 &&
(get_exec_type_size(inst) == 8 || type_sz(inst->dst.type) == 8))
lowered_width = MIN2(lowered_width, 4);

4
src/intel/compiler/brw_vec4_generator.cpp
View File

@@ -1521,7 +1521,7 @@ generate_code(struct brw_codegen *p,
inst->opcode != VEC4_OPCODE_SET_HIGH_32BIT;
unsigned exec_size = inst->exec_size;
if (devinfo->ver == 7 && !devinfo->is_haswell && is_df)
if (devinfo->verx10 == 70 && is_df)
exec_size *= 2;
brw_set_default_exec_size(p, cvt(exec_size) - 1);
@@ -1955,7 +1955,7 @@ generate_code(struct brw_codegen *p,
* need to explicitly set stride 2, but 1.
*/
struct brw_reg spread_dst;
if (devinfo->ver == 7 && !devinfo->is_haswell)
if (devinfo->verx10 == 70)
spread_dst = stride(dst, 8, 4, 1);
else
spread_dst = stride(dst, 8, 4, 2);

2
src/intel/compiler/test_eu_validate.cpp
View File

@@ -833,7 +833,7 @@ TEST_P(validation_test, vstride_on_align16_must_be_0_or_4)
} vstride[] = {
{ BRW_VERTICAL_STRIDE_0, true },
{ BRW_VERTICAL_STRIDE_1, false },
{ BRW_VERTICAL_STRIDE_2, devinfo.is_haswell || devinfo.ver >= 8 },
{ BRW_VERTICAL_STRIDE_2, devinfo.verx10 >= 75 },
{ BRW_VERTICAL_STRIDE_4, true },
{ BRW_VERTICAL_STRIDE_8, false },
{ BRW_VERTICAL_STRIDE_16, false },

18
src/intel/isl/isl_storage_image.c
View File

@@ -108,7 +108,7 @@ isl_lower_storage_image_format(const struct intel_device_info *devinfo,
case ISL_FORMAT_R32G32_SINT:
case ISL_FORMAT_R32G32_FLOAT:
return (devinfo->ver >= 9 ? format :
devinfo->ver >= 8 || devinfo->is_haswell ?
devinfo->verx10 >= 75 ?
ISL_FORMAT_R16G16B16A16_UINT :
ISL_FORMAT_R32G32_UINT);
@@ -125,20 +125,20 @@ isl_lower_storage_image_format(const struct intel_device_info *devinfo,
case ISL_FORMAT_R8G8B8A8_UINT:
case ISL_FORMAT_R8G8B8A8_SINT:
return (devinfo->ver >= 9 ? format :
devinfo->ver >= 8 || devinfo->is_haswell ?
devinfo->verx10 >= 75 ?
ISL_FORMAT_R8G8B8A8_UINT : ISL_FORMAT_R32_UINT);
case ISL_FORMAT_R16G16_UINT:
case ISL_FORMAT_R16G16_SINT:
case ISL_FORMAT_R16G16_FLOAT:
return (devinfo->ver >= 9 ? format :
devinfo->ver >= 8 || devinfo->is_haswell ?
devinfo->verx10 >= 75 ?
ISL_FORMAT_R16G16_UINT : ISL_FORMAT_R32_UINT);
case ISL_FORMAT_R8G8_UINT:
case ISL_FORMAT_R8G8_SINT:
return (devinfo->ver >= 9 ? format :
devinfo->ver >= 8 || devinfo->is_haswell ?
devinfo->verx10 >= 75 ?
ISL_FORMAT_R8G8_UINT : ISL_FORMAT_R16_UINT);
case ISL_FORMAT_R16_UINT:
@@ -162,26 +162,26 @@ isl_lower_storage_image_format(const struct intel_device_info *devinfo,
case ISL_FORMAT_R16G16B16A16_UNORM:
case ISL_FORMAT_R16G16B16A16_SNORM:
return (devinfo->ver >= 11 ? format :
devinfo->ver >= 8 || devinfo->is_haswell ?
devinfo->verx10 >= 75 ?
ISL_FORMAT_R16G16B16A16_UINT :
ISL_FORMAT_R32G32_UINT);
case ISL_FORMAT_R8G8B8A8_UNORM:
case ISL_FORMAT_R8G8B8A8_SNORM:
return (devinfo->ver >= 11 ? format :
devinfo->ver >= 8 || devinfo->is_haswell ?
devinfo->verx10 >= 75 ?
ISL_FORMAT_R8G8B8A8_UINT : ISL_FORMAT_R32_UINT);
case ISL_FORMAT_R16G16_UNORM:
case ISL_FORMAT_R16G16_SNORM:
return (devinfo->ver >= 11 ? format :
devinfo->ver >= 8 || devinfo->is_haswell ?
devinfo->verx10 >= 75 ?
ISL_FORMAT_R16G16_UINT : ISL_FORMAT_R32_UINT);
case ISL_FORMAT_R8G8_UNORM:
case ISL_FORMAT_R8G8_SNORM:
return (devinfo->ver >= 11 ? format :
devinfo->ver >= 8 || devinfo->is_haswell ?
devinfo->verx10 >= 75 ?
ISL_FORMAT_R8G8_UINT : ISL_FORMAT_R16_UINT);
case ISL_FORMAT_R16_UNORM:
@@ -204,7 +204,7 @@ isl_has_matching_typed_storage_image_format(const struct intel_device_info *devi
{
if (devinfo->ver >= 9) {
return true;
} else if (devinfo->ver >= 8 || devinfo->is_haswell) {
} else if (devinfo->verx10 >= 75) {
return isl_format_get_layout(fmt)->bpb <= 64;
} else {
return isl_format_get_layout(fmt)->bpb <= 32;

2
src/intel/vulkan/anv_descriptor_set.c
View File

@@ -110,7 +110,7 @@ anv_descriptor_data_for_type(const struct anv_physical_device *device,
* VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT because they already must
* have identity swizzle.
*/
if (device->info.ver == 7 && !device->info.is_haswell &&
if (device->info.verx10 == 70 &&
(type == VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE ||
type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER))
data |= ANV_DESCRIPTOR_TEXTURE_SWIZZLE;

2
src/intel/vulkan/anv_device.c
View File

@@ -1801,7 +1801,7 @@ void anv_GetPhysicalDeviceProperties(
pdevice->has_bindless_images ? UINT16_MAX : 128;
const uint32_t max_samplers =
pdevice->has_bindless_samplers ? UINT16_MAX :
(devinfo->ver >= 8 || devinfo->is_haswell) ? 128 : 16;
(devinfo->verx10 >= 75) ? 128 : 16;
const uint32_t max_images =
pdevice->has_bindless_images ? UINT16_MAX : MAX_IMAGES;

2
src/intel/vulkan/anv_formats.c
View File

@@ -507,7 +507,7 @@ anv_get_format_plane(const struct intel_device_info *devinfo,
* can reliably do texture upload with BLORP so just don't claim support
* for any of them.
*/
if (devinfo->ver == 7 && !devinfo->is_haswell &&
if (devinfo->verx10 == 70 &&
(isl_layout->bpb == 24 || isl_layout->bpb == 48))
return unsupported;

4
src/intel/vulkan/anv_image.c
View File

@@ -2376,7 +2376,7 @@ anv_layout_to_fast_clear_type(const struct intel_device_info * const devinfo,
/* We don't support MSAA fast-clears on Ivybridge or Bay Trail because they
* lack the MI ALU which we need to determine the predicates.
*/
if (devinfo->ver == 7 && !devinfo->is_haswell && image->samples > 1)
if (devinfo->verx10 == 70 && image->samples > 1)
return ANV_FAST_CLEAR_NONE;
enum isl_aux_state aux_state =
@@ -2500,7 +2500,7 @@ anv_image_fill_surface_state(struct anv_device *device,
view.swizzle = anv_swizzle_for_render(view.swizzle);
/* On Ivy Bridge and Bay Trail we do the swizzle in the shader */
if (device->info.ver == 7 && !device->info.is_haswell)
if (device->info.verx10 == 70)
view.swizzle = ISL_SWIZZLE_IDENTITY;
/* If this is a HiZ buffer we can sample from with a programmable clear

4
src/mesa/drivers/dri/i965/brw_context.c
View File

@@ -409,7 +409,7 @@ brw_init_driver_functions(struct brw_context *brw,
brw_init_frag_prog_functions(functions);
brw_init_common_queryobj_functions(functions);
if (devinfo->ver >= 8 || devinfo->is_haswell)
if (devinfo->verx10 >= 75)
hsw_init_queryobj_functions(functions);
else if (devinfo->ver >= 6)
gfx6_init_queryobj_functions(functions);
@@ -518,7 +518,7 @@ brw_initialize_context_constants(struct brw_context *brw)
}
unsigned max_samplers =
devinfo->ver >= 8 || devinfo->is_haswell ? BRW_MAX_TEX_UNIT : 16;
devinfo->verx10 >= 75 ? BRW_MAX_TEX_UNIT : 16;
ctx->Const.MaxDualSourceDrawBuffers = 1;
ctx->Const.MaxDrawBuffers = BRW_MAX_DRAW_BUFFERS;

2
src/mesa/drivers/dri/i965/brw_draw.c
View File

@@ -336,7 +336,7 @@ brw_merge_inputs(struct brw_context *brw)
const struct intel_device_info *devinfo = &brw->screen->devinfo;
const struct gl_context *ctx = &brw->ctx;
if (devinfo->ver < 8 && !devinfo->is_haswell) {
if (devinfo->verx10 <= 70) {
/* Prior to Haswell, the hardware can't natively support GL_FIXED or
* 2_10_10_10_REV vertex formats. Set appropriate workaround flags.
*/

12
src/mesa/drivers/dri/i965/brw_draw_upload.c
View File

@@ -315,7 +315,7 @@ brw_get_vertex_surface_type(struct brw_context *brw,
return ubyte_types_norm[size];
}
case GL_FIXED:
if (devinfo->ver >= 8 || devinfo->is_haswell)
if (devinfo->verx10 >= 75)
return fixed_point_types[size];
/* This produces GL_FIXED inputs as values between INT32_MIN and
@@ -329,7 +329,7 @@ brw_get_vertex_surface_type(struct brw_context *brw,
*/
case GL_INT_2_10_10_10_REV:
assert(size == 4);
if (devinfo->ver >= 8 || devinfo->is_haswell) {
if (devinfo->verx10 >= 75) {
return glformat->Format == GL_BGRA
? ISL_FORMAT_B10G10R10A2_SNORM
: ISL_FORMAT_R10G10B10A2_SNORM;
@@ -337,7 +337,7 @@ brw_get_vertex_surface_type(struct brw_context *brw,
return ISL_FORMAT_R10G10B10A2_UINT;
case GL_UNSIGNED_INT_2_10_10_10_REV:
assert(size == 4);
if (devinfo->ver >= 8 || devinfo->is_haswell) {
if (devinfo->verx10 >= 75) {
return glformat->Format == GL_BGRA
? ISL_FORMAT_B10G10R10A2_UNORM
: ISL_FORMAT_R10G10B10A2_UNORM;
@@ -354,7 +354,7 @@ brw_get_vertex_surface_type(struct brw_context *brw,
*/
if (glformat->Type == GL_INT_2_10_10_10_REV) {
assert(size == 4);
if (devinfo->ver >= 8 || devinfo->is_haswell) {
if (devinfo->verx10 >= 75) {
return glformat->Format == GL_BGRA
? ISL_FORMAT_B10G10R10A2_SSCALED
: ISL_FORMAT_R10G10B10A2_SSCALED;
@@ -362,7 +362,7 @@ brw_get_vertex_surface_type(struct brw_context *brw,
return ISL_FORMAT_R10G10B10A2_UINT;
} else if (glformat->Type == GL_UNSIGNED_INT_2_10_10_10_REV) {
assert(size == 4);
if (devinfo->ver >= 8 || devinfo->is_haswell) {
if (devinfo->verx10 >= 75) {
return glformat->Format == GL_BGRA
? ISL_FORMAT_B10G10R10A2_USCALED
: ISL_FORMAT_R10G10B10A2_USCALED;
@@ -386,7 +386,7 @@ brw_get_vertex_surface_type(struct brw_context *brw,
case GL_UNSIGNED_SHORT: return ushort_types_scale[size];
case GL_UNSIGNED_BYTE: return ubyte_types_scale[size];
case GL_FIXED:
if (devinfo->ver >= 8 || devinfo->is_haswell)
if (devinfo->verx10 >= 75)
return fixed_point_types[size];
/* This produces GL_FIXED inputs as values between INT32_MIN and

6
src/mesa/drivers/dri/i965/brw_extensions.c
View File

@@ -271,7 +271,7 @@ brw_init_extensions(struct gl_context *ctx)
ctx->Const.MaxComputeWorkGroupSize[0] >= 1024) {
ctx->Extensions.ARB_compute_shader = true;
ctx->Extensions.ARB_ES3_1_compatibility =
devinfo->ver >= 8 || devinfo->is_haswell;
devinfo->verx10 >= 75;
ctx->Extensions.NV_compute_shader_derivatives = true;
ctx->Extensions.ARB_compute_variable_group_size = true;
}
@@ -286,7 +286,7 @@ brw_init_extensions(struct gl_context *ctx)
ctx->Extensions.ARB_spirv_extensions = true;
}
if (devinfo->ver >= 8 || devinfo->is_haswell) {
if (devinfo->verx10 >= 75) {
ctx->Extensions.ARB_stencil_texturing = true;
ctx->Extensions.ARB_texture_stencil8 = true;
ctx->Extensions.OES_geometry_shader = true;
@@ -294,7 +294,7 @@ brw_init_extensions(struct gl_context *ctx)
ctx->Extensions.OES_viewport_array = true;
}
if (devinfo->ver >= 8 || devinfo->is_haswell || devinfo->is_baytrail) {
if (devinfo->verx10 >= 75 || devinfo->is_baytrail) {
ctx->Extensions.ARB_robust_buffer_access_behavior = true;
}

2
src/mesa/drivers/dri/i965/brw_mipmap_tree.c
View File

@@ -1488,7 +1488,7 @@ brw_miptree_level_enable_hiz(struct brw_context *brw,
assert(mt->aux_buf);
assert(mt->surf.size_B > 0);
if (devinfo->ver >= 8 || devinfo->is_haswell) {
if (devinfo->verx10 >= 75) {
uint32_t width = minify(mt->surf.phys_level0_sa.width, level);
uint32_t height = minify(mt->surf.phys_level0_sa.height, level);

2
src/mesa/drivers/dri/i965/brw_misc_state.c
View File

@@ -561,7 +561,7 @@ brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline)
(pipeline == BRW_COMPUTE_PIPELINE ? 2 : 0));
ADVANCE_BATCH();
if (devinfo->ver == 7 && !devinfo->is_haswell &&
if (devinfo->verx10 == 70 &&
pipeline == BRW_RENDER_PIPELINE) {
/* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
* PIPELINE_SELECT [DevBWR+]":

2
src/mesa/drivers/dri/i965/brw_primitive_restart.c
View File

@@ -353,7 +353,7 @@ can_cut_index_handle_prims(struct gl_context *ctx,
const struct intel_device_info *devinfo = &brw->screen->devinfo;
/* Otherwise Haswell can do it all. */
if (devinfo->ver >= 8 || devinfo->is_haswell)
if (devinfo->verx10 >= 75)
return true;
if (!can_cut_index_handle_restart_index(ctx, ib, restart_index)) {

4
src/mesa/drivers/dri/i965/brw_program.c
View File

@@ -376,7 +376,7 @@ brw_memory_barrier(struct gl_context *ctx, GLbitfield barriers)
/* Typed surface messages are handled by the render cache on IVB, so we
* need to flush it too.
*/
if (devinfo->ver == 7 && !devinfo->is_haswell)
if (devinfo->verx10 == 70)
bits |= PIPE_CONTROL_RENDER_TARGET_FLUSH;
brw_emit_pipe_control_flush(brw, bits);
@@ -827,7 +827,7 @@ brw_setup_tex_for_precompile(const struct intel_device_info *devinfo,
struct brw_sampler_prog_key_data *tex,
const struct gl_program *prog)
{
const bool has_shader_channel_select = devinfo->is_haswell || devinfo->ver >= 8;
const bool has_shader_channel_select = devinfo->verx10 >= 75;
unsigned sampler_count = util_last_bit(prog->SamplersUsed);
for (unsigned i = 0; i < sampler_count; i++) {
if (!has_shader_channel_select && (prog->ShadowSamplers & (1 << i))) {

2
src/mesa/drivers/dri/i965/brw_vs.c
View File

@@ -294,7 +294,7 @@ brw_vs_populate_key(struct brw_context *brw,
}
/* BRW_NEW_VS_ATTRIB_WORKAROUNDS */
if (devinfo->ver < 8 && !devinfo->is_haswell) {
if (devinfo->verx10 <= 70) {
memcpy(key->gl_attrib_wa_flags, brw->vb.attrib_wa_flags,
sizeof(brw->vb.attrib_wa_flags));
}

2
src/mesa/drivers/dri/i965/brw_wm.c
View File

@@ -225,7 +225,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx,
/* Haswell handles texture swizzling as surface format overrides
* (except for GL_ALPHA); all other platforms need MOVs in the shader.
*/
if (alpha_depth || (devinfo->ver < 8 && !devinfo->is_haswell))
if (alpha_depth || (devinfo->verx10 <= 70))
key->swizzles[s] = brw_get_texture_swizzle(ctx, t);
if (devinfo->ver < 8 &&

2
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
View File

@@ -603,7 +603,7 @@ static void brw_update_texture_surface(struct gl_context *ctx,
/* On Ivy Bridge and earlier, we handle texture swizzle with shader
* code. The actual surface swizzle should be identity.
*/
if (devinfo->ver <= 7 && !devinfo->is_haswell)
if (devinfo->verx10 <= 70)
view.swizzle = ISL_SWIZZLE_IDENTITY;
if (obj->Target == GL_TEXTURE_CUBE_MAP ||

2
src/mesa/drivers/dri/i965/gfx6_constant_state.c
View File

@@ -156,7 +156,7 @@ gfx6_upload_push_constants(struct brw_context *brw,
int i;
const int size = prog_data->nr_params * sizeof(gl_constant_value);
gl_constant_value *param;
if (devinfo->ver >= 8 || devinfo->is_haswell) {
if (devinfo->verx10 >= 75) {
param = brw_upload_space(&brw->upload, size, 32,
&stage_state->push_const_bo,
&stage_state->push_const_offset);

4
src/mesa/drivers/dri/i965/gfx7_urb.c
View File

@@ -173,7 +173,7 @@ gfx7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,
*
* No such restriction exists for Haswell or Baytrail.
*/
if (devinfo->ver < 8 && !devinfo->is_haswell && !devinfo->is_baytrail)
if (devinfo->verx10 <= 70 && !devinfo->is_baytrail)
gfx7_emit_cs_stall_flush(brw);
}
@@ -252,7 +252,7 @@ gfx7_upload_urb(struct brw_context *brw, unsigned vs_size,
tess_present, gs_present, entry_size,
entries, start, NULL, &constrained);
if (devinfo->ver == 7 && !devinfo->is_haswell && !devinfo->is_baytrail)
if (devinfo->verx10 == 70 && !devinfo->is_baytrail)
gfx7_emit_vs_workaround_flush(brw);
BEGIN_BATCH(8);