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nouveau/mme: Stop using isaspec

Browse Source 
We had hand-written decoders for the simulators anyway so it really
isn't gaining us much.  It does, however, make the whole build more
complicated.  Better to just drop it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27126>
This commit is contained in:
Faith Ekstrand
2024-01-17 14:02:16 -06:00
committed by Marge Bot
parent a69b7f1b19
commit 32f2a0f1e1
8 changed files with 196 additions and 584 deletions
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63
src/nouveau/mme/meson.build
View File

@@ -1,87 +1,26 @@
# Copyright © 2022 Collabora, Ltd.
# SPDX-License-Identifier: MIT
mme_tu104_isa_depend_files = [
'mme_tu104.xml',
isaspec_py_deps
]
mme_tu104_isa = custom_target(
'mme_isa',
input: ['mme_tu104.xml'],
output: ['mme_tu104_isa.c', 'mme_tu104_isa.h'],
command: [
prog_isaspec_decode, '--xml', '@INPUT@',
'--out-c', '@OUTPUT0@', '--out-h', '@OUTPUT1@',
],
depend_files: mme_tu104_isa_depend_files,
)
mme_tu104_encode_h = custom_target(
'mme-tu104-encode.h',
input: ['mme_tu104.xml'],
output: 'mme_tu104_encode.h',
command: [
prog_isaspec_encode, '--xml', '@INPUT@', '--out-h', '@OUTPUT@'
],
depend_files: mme_tu104_isa_depend_files,
)
mme_fermi_isa_depend_files = [
'mme_fermi.xml',
isaspec_py_deps
]
mme_fermi_isa = custom_target(
'mme_fermi_isa',
input: ['mme_fermi.xml'],
output: ['mme_fermi_isa.c', 'mme_fermi_isa.h'],
command: [
prog_isaspec_decode, '--xml', '@INPUT@',
'--out-c', '@OUTPUT0@', '--out-h', '@OUTPUT1@',
],
depend_files: mme_fermi_isa_depend_files,
)
mme_fermi_encode_h = custom_target(
'mme-fermi-encode.h',
input: ['mme_fermi.xml'],
output: 'mme_fermi_encode.h',
command: [
prog_isaspec_encode, '--xml', '@INPUT@', '--out-h', '@OUTPUT@'
],
depend_files: mme_fermi_isa_depend_files,
)
libnouveau_mme_files = files(
'mme_builder.h',
'mme_fermi.c',
'mme_fermi.h',
'mme_fermi_builder.c',
'mme_fermi_dump.c',
'mme_fermi_sim.c',
'mme_tu104.c',
'mme_tu104.h',
'mme_tu104_builder.c',
'mme_tu104_dump.c',
'mme_tu104_sim.c',
'mme_tu104_sim.h',
)
_libnouveau_mme = static_library(
'nouveau_mme',
[
libnouveau_mme_files,
mme_fermi_isa,
mme_fermi_encode_h,
mme_tu104_isa,
mme_tu104_encode_h,
],
libnouveau_mme_files,
include_directories : [inc_include, inc_src],
gnu_symbol_visibility : 'hidden',
dependencies : [
idep_mesautil,
idep_isaspec_decode,
idep_nvidia_headers,
],
)

71
src/nouveau/mme/mme_bitpack_helpers.h Normal file
View File

@@ -0,0 +1,71 @@
/*
* Copyright © 2024 Collabora, Ltd.
* SPDX-License-Identifier: MIT
*/
#ifndef MME_BITPACK_HELPERS_H
#define MME_BITPACK_HELPERS_H
#include "util/bitpack_helpers.h"
#include "util/u_math.h"
static inline void
pack_uint(uint32_t *b, unsigned start, unsigned end, uint64_t data)
{
assert(end >= start);
uint32_t dw = start / 32;
start -= dw * 32;
end -= dw * 32;
assert(end < 64);
uint64_t packed = util_bitpack_uint(data, start, end);
b[dw] |= packed;
if (end >= 32)
b[dw + 1] |= packed >> 32;
}
static inline void
pack_sint(uint32_t *b, unsigned start, unsigned end, int64_t data)
{
assert(end >= start);
uint32_t dw = start / 32;
start -= dw * 32;
end -= dw * 32;
assert(end < 64);
uint64_t packed = util_bitpack_sint(data, start, end);
b[dw] |= packed;
if (end >= 32)
b[dw + 1] |= packed >> 32;
}
static inline uint64_t
unpack_uint(const uint32_t *b, unsigned start, unsigned end)
{
assert(end >= start);
uint32_t dw = start / 32;
start -= dw * 32;
end -= dw * 32;
assert(end < 64);
uint64_t packed = b[dw];
if (end >= 32)
packed |= (uint64_t)b[dw + 1] << 32;
packed &= util_bitpack_ones(start, end);
return packed >> start;
}
static inline uint64_t
unpack_sint(const uint32_t *b, unsigned start, unsigned end)
{
unsigned bits = end - start + 1;
return util_sign_extend(unpack_uint(b, start, end), bits);
}
#endif /* MME_BITPACK_HELPERS_H */

108
src/nouveau/mme/mme_fermi.c
View File

@@ -3,9 +3,8 @@
* SPDX-License-Identifier: MIT
*/
#include "mme_fermi.h"
#include "mme_fermi_encode.h"
#include "util/u_math.h"
#include "mme_bitpack_helpers.h"
#define OP_TO_STR(OP) [MME_FERMI_OP_##OP] = #OP
static const char *op_to_str[] = {
@@ -95,67 +94,77 @@ void mme_fermi_encode(uint32_t *out, uint32_t inst_count,
const struct mme_fermi_inst *insts)
{
for (uint32_t i = 0; i < inst_count; i++) {
bitmask_t enc = encode__instruction(NULL, NULL, insts[i]);
out[i] = enc.bitset[0];
uint32_t *b = &out[i];
*b = 0;
pack_uint(b, 0, 3, insts[i].op);
pack_uint(b, 7, 7, insts[i].end_next);
pack_uint(b, 8, 10, insts[i].dst);
if (insts[i].op != MME_FERMI_OP_BRANCH) {
pack_uint(b, 4, 6, insts[i].assign_op);
}
if (insts[i].op == MME_FERMI_OP_ALU_REG) {
pack_uint(b, 11, 13, insts[i].src[0]);
pack_uint(b, 14, 16, insts[i].src[1]);
pack_uint(b, 17, 21, insts[i].alu_op);
} else if (insts[i].op == MME_FERMI_OP_ADD_IMM ||
insts[i].op == MME_FERMI_OP_STATE) {
pack_uint(b, 11, 13, insts[i].src[0]);
pack_sint(b, 14, 31, insts[i].imm);
} else if (insts[i].op == MME_FERMI_OP_MERGE ||
insts[i].op == MME_FERMI_OP_BFE_LSL_IMM ||
insts[i].op == MME_FERMI_OP_BFE_LSL_REG) {
pack_uint(b, 11, 13, insts[i].src[0]);
pack_uint(b, 14, 16, insts[i].src[1]);
pack_uint(b, 17, 21, insts[i].bitfield.src_bit);
pack_uint(b, 22, 26, insts[i].bitfield.size);
pack_uint(b, 27, 31, insts[i].bitfield.dst_bit);
} else if (insts[i].op == MME_FERMI_OP_BRANCH) {
pack_uint(b, 4, 4, insts[i].branch.not_zero);
pack_uint(b, 5, 5, insts[i].branch.no_delay);
pack_uint(b, 11, 13, insts[i].src[0]);
pack_sint(b, 14, 31, insts[i].imm);
}
}
}
static uint64_t
unpack_field(bitmask_t bitmask, unsigned low, unsigned high, bool is_signed)
{
bitmask_t field, mask;
assert(high >= low);
BITSET_ZERO(mask.bitset);
BITSET_SET_RANGE(mask.bitset, 0, high - low);
BITSET_COPY(field.bitset, bitmask.bitset);
BITSET_SHR(field.bitset, low);
BITSET_AND(field.bitset, field.bitset, mask.bitset);
uint64_t data = bitmask_to_uint64_t(field);
if (is_signed)
data = util_sign_extend(data, high - low + 1);
return data;
}
void mme_fermi_decode(struct mme_fermi_inst *insts,
const uint32_t *in, uint32_t inst_count)
{
for (uint32_t i = 0; i < inst_count; i++) {
bitmask_t enc = { .bitset = { in[i] }};
const uint32_t *b = &in[i];
insts[i].op = unpack_field(enc, 0, 3, false);
insts[i].end_next = unpack_field(enc, 7, 7, false);
insts[i].dst = unpack_field(enc, 8, 10, false);
insts[i].op = unpack_uint(b, 0, 3);
insts[i].end_next = unpack_uint(b, 7, 7);
insts[i].dst = unpack_uint(b, 8, 10);
if (insts[i].op != MME_FERMI_OP_BRANCH) {
insts[i].assign_op = unpack_field(enc, 4, 6, false);
insts[i].assign_op = unpack_uint(b, 4, 6);
}
if (insts[i].op == MME_FERMI_OP_ALU_REG) {
insts[i].src[0] = unpack_field(enc, 11, 13, false);
insts[i].src[1] = unpack_field(enc, 14, 16, false);
insts[i].alu_op = unpack_field(enc, 17, 21, false);
insts[i].src[0] = unpack_uint(b, 11, 13);
insts[i].src[1] = unpack_uint(b, 14, 16);
insts[i].alu_op = unpack_uint(b, 17, 21);
} else if (insts[i].op == MME_FERMI_OP_ADD_IMM ||
insts[i].op == MME_FERMI_OP_STATE) {
insts[i].src[0] = unpack_field(enc, 11, 13, false);
insts[i].imm = unpack_field(enc, 14, 31, false);
insts[i].src[0] = unpack_uint(b, 11, 13);
insts[i].imm = unpack_sint(b, 14, 31);
} else if (insts[i].op == MME_FERMI_OP_MERGE ||
insts[i].op == MME_FERMI_OP_BFE_LSL_IMM ||
insts[i].op == MME_FERMI_OP_BFE_LSL_REG) {
insts[i].src[0] = unpack_field(enc, 11, 13, false);
insts[i].src[1] = unpack_field(enc, 14, 16, false);
insts[i].bitfield.src_bit = unpack_field(enc, 17, 21, false);
insts[i].bitfield.size = unpack_field(enc, 22, 26, false);
insts[i].bitfield.dst_bit = unpack_field(enc, 27, 31, false);
insts[i].src[0] = unpack_uint(b, 11, 13);
insts[i].src[1] = unpack_uint(b, 14, 16);
insts[i].bitfield.src_bit = unpack_uint(b, 17, 21);
insts[i].bitfield.size = unpack_uint(b, 22, 26);
insts[i].bitfield.dst_bit = unpack_uint(b, 27, 31);
} else if (insts[i].op == MME_FERMI_OP_BRANCH) {
insts[i].branch.not_zero = unpack_field(enc, 4, 4, false);
insts[i].branch.no_delay = unpack_field(enc, 5, 5, false);
insts[i].src[0] = unpack_field(enc, 11, 13, false);
insts[i].imm = unpack_field(enc, 14, 31, false);
insts[i].branch.not_zero = unpack_uint(b, 4, 4);
insts[i].branch.no_delay = unpack_uint(b, 5, 5);
insts[i].src[0] = unpack_uint(b, 11, 13);
insts[i].imm = unpack_sint(b, 14, 31);
}
}
}
@@ -281,3 +290,14 @@ mme_fermi_print(FILE *fp, const struct mme_fermi_inst *insts,
mme_fermi_print_inst(fp, 1, &insts[i]);
}
}
void
mme_fermi_dump(FILE *fp, uint32_t *encoded, size_t encoded_size)
{
uint32_t inst_count = encoded_size / 4;
for (uint32_t i = 0; i < inst_count; i++) {
struct mme_fermi_inst inst;
mme_fermi_decode(&inst, &encoded[i], 1);
mme_fermi_print_inst(fp, 1, &inst);
}
}

201
src/nouveau/mme/mme_fermi.xml
View File

@@ -1,201 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<!--
Copyright © 2022 Mary Guillemard
SPDX-License-Identifier: MIT
-->
<isa>
<enum name="#reg">
<value val="0" display="zero"/>
<value val="1" display="r1"/>
<value val="2" display="r2"/>
<value val="3" display="r3"/>
<value val="4" display="r4"/>
<value val="5" display="r5"/>
<value val="6" display="r6"/>
<value val="7" display="r7"/>
</enum>
<enum name="#op">
<value val="0" display="ALU_REG"/>
<value val="1" display="ADD_IMM"/>
<value val="2" display="MERGE"/>
<value val="3" display="BFE_LSL_IMM"/>
<value val="4" display="BFE_LSL_REG"/>
<value val="5" display="STATE"/>
<!-- TODO: There seems to be something here (no fault is generated) -->
<value val="6" display="UNK6"/>
<value val="7" display="BRANCH"/>
</enum>
<enum name="#alu-op">
<value val="0" display="ADD"/>
<value val="1" display="ADDC"/>
<value val="2" display="SUB"/>
<value val="3" display="SUBB"/>
<!-- value val="4" display="reserved4"/ -->
<!-- value val="5" display="reserved5"/ -->
<!-- value val="6" display="reserved6"/ -->
<!-- value val="7" display="reserved7"/ -->
<value val="8" display="XOR"/>
<value val="9" display="OR"/>
<value val="10" display="AND"/>
<value val="11" display="AND_NOT"/>
<value val="12" display="NAND"/>
<!-- value val="13" display="reserved13"/ -->
<!-- value val="14" display="reserved14"/ -->
<!-- value val="15" display="reserved15"/ -->
<!-- value val="16" display="reserved16"/ -->
<!-- value val="17" display="reserved17"/ -->
<!-- value val="18" display="reserved18"/ -->
<!-- value val="19" display="reserved19"/ -->
<!-- value val="20" display="reserved20"/ -->
<!-- value val="21" display="reserved21"/ -->
<!-- value val="22" display="reserved22"/ -->
<!-- value val="23" display="reserved23"/ -->
<!-- value val="24" display="reserved24"/ -->
<!-- value val="25" display="reserved25"/ -->
<!-- value val="26" display="reserved26"/ -->
<!-- value val="27" display="reserved27"/ -->
<!-- value val="28" display="reserved28"/ -->
<!-- value val="29" display="reserved29"/ -->
<!-- value val="30" display="reserved30"/ -->
<!-- value val="31" display="reserved31"/ -->
</enum>
<enum name="#assign-op">
<value val="0" display="LOAD"/>
<value val="1" display="MOVE"/>
<value val="2" display="MOVE_SET_MADDR"/>
<value val="3" display="LOAD_EMIT"/>
<value val="4" display="MOVE_EMIT"/>
<value val="5" display="LOAD_SET_MADDR"/>
<value val="6" display="MOVE_SET_MADDR_LOAD_EMIT"/>
<value val="7" display="MOVE_SET_MADDR_LOAD_EMIT_HIGH"/>
</enum>
<bitset name="#alu-instruction" size="18">
<display>
{NAME} {ASSIGN_OP} {ALU_OP} {DST} {SRC0} {SRC1}
</display>
<field name="ASSIGN_OP" low="0" high="2" type="#assign-op"/>
<pattern low="3" high="3">x</pattern>
<field name="DST" low="4" high="6" type="#reg"/>
<field name="SRC0" low="7" high="9" type="#reg"/>
<field name="SRC1" low="10" high="12" type="#reg"/>
<field name="ALU_OP" low="13" high="17" type="#alu-op"/>
<encode type="struct mme_fermi_inst">
<map name="ASSIGN_OP">src.assign_op</map>
<map name="ALU_OP">src.alu_op</map>
<map name="DST">src.dst</map>
<map name="SRC0">src.src[0]</map>
<map name="SRC1">src.src[1]</map>
</encode>
</bitset>
<bitset name="#src0-imm-encoding" size="28">
<display>
{NAME} {ASSIGN_OP} {DST} {SRC0} {IMM}
</display>
<field name="ASSIGN_OP" low="0" high="2" type="#assign-op"/>
<pattern low="3" high="3">x</pattern>
<field name="DST" low="4" high="6" type="#reg"/>
<field name="SRC0" low="7" high="9" type="#reg"/>
<field name="IMM" low="10" high="27" type="int"/>
<encode type="struct mme_fermi_inst">
<map name="ASSIGN_OP">src.assign_op</map>
<map name="DST">src.dst</map>
<map name="SRC0">src.src[0]</map>
<map name="IMM">src.imm</map>
</encode>
</bitset>
<bitset name="#bf-encoding" size="28">
<display>
{NAME} {ASSIGN_OP} {DST} {SRC0} {SRC1} {BF_SRC_BIT} {BF_SIZE} {BF_DST_BIT}
</display>
<field name="ASSIGN_OP" low="0" high="2" type="#assign-op"/>
<pattern low="3" high="3">x</pattern>
<field name="DST" low="4" high="6" type="#reg"/>
<field name="SRC0" low="7" high="9" type="#reg"/>
<field name="SRC1" low="10" high="12" type="#reg"/>
<field name="BF_SRC_BIT" low="13" high="17" type="uint"/>
<field name="BF_SIZE" low="18" high="22" type="uint"/>
<field name="BF_DST_BIT" low="23" high="27" type="uint"/>
<encode type="struct mme_fermi_inst">
<map name="ASSIGN_OP">src.assign_op</map>
<map name="DST">src.dst</map>
<map name="SRC0">src.src[0]</map>
<map name="SRC1">src.src[1]</map>
<map name="BF_SRC_BIT">src.bitfield.src_bit</map>
<map name="BF_SIZE">src.bitfield.size</map>
<map name="BF_DST_BIT">src.bitfield.dst_bit</map>
</encode>
</bitset>
<bitset name="#branch-encoding" size="28">
<display>
{NO_DELAY} B{NOT_ZERO} {SRC0} {IMM}
</display>
<field name="NOT_ZERO" pos="0" type="bool" display="Z"/>
<field name="NO_DELAY" pos="1" type="bool" display="NO_DELAY"/>
<pattern low="2" high="6">xxxxx</pattern>
<field name="SRC0" low="7" high="9" type="#reg"/>
<field name="IMM" low="10" high="27" type="int"/>
<encode type="struct mme_fermi_inst">
<map name="NOT_ZERO">src.branch.not_zero</map>
<map name="NO_DELAY">src.branch.no_delay</map>
<map name="SRC0">src.src[0]</map>
<map name="IMM">src.imm</map>
</encode>
</bitset>
<bitset name="#instruction" size="32">
<doc>
Encoding of a NVIDIA Fermi Macro Method instruction. All instructions are 32b.
</doc>
<display>
{END_NEXT} {OP} {ALU_OP_ENCODING} {SRC0_IMM_ENCODING} {BF_ENCODING} {BRANCH_ENCODING}
</display>
<field name="OP" low="0" high="3" type="#op"/>
<pattern low="4" high="6">xxx</pattern>
<field name="END_NEXT" pos="7" type="bool" display="(end-next)"/>
<pattern low="8" high="31">xxxxxxxxxxxxxxxxxxxxxxxx</pattern>
<override>
<expr>{OP} == 0</expr>
<field name="ALU_OP_ENCODING" low="4" high="21" type="#alu-instruction" />
</override>
<override>
<expr>{OP} == 1 || {OP} == 5</expr>
<field name="SRC0_IMM_ENCODING" low="4" high="31" type="#src0-imm-encoding" />
</override>
<override>
<expr>{OP} == 2 || {OP} == 3 || {OP} == 4</expr>
<field name="BF_ENCODING" low="4" high="31" type="#bf-encoding" />
</override>
<override>
<expr>{OP} == 7</expr>
<field name="BRANCH_ENCODING" low="4" high="31" type="#branch-encoding" />
</override>
<encode type="struct mme_fermi_inst">
<map name="END_NEXT">src.end_next</map>
<map name="OP">src.op</map>
<map name="ALU_OP_ENCODING">src</map>
<map name="SRC0_IMM_ENCODING">src</map>
<map name="BF_ENCODING">src</map>
<map name="BRANCH_ENCODING">src</map>
</encode>
</bitset>
</isa>

28
src/nouveau/mme/mme_fermi_dump.c
View File

@@ -1,28 +0,0 @@
/*
* Copyright © 2022 Mary Guillemard
* SPDX-License-Identifier: MIT
*/
#include "mme_fermi.h"
#include "mme_fermi_isa.h"
#include "isa.h"
#include <stdlib.h>
static void
disasm_instr_cb(void *d, unsigned n, void *instr)
{
fprintf(d, "%3d[%08x]", n, *(uint32_t *)instr);
}
void
mme_fermi_dump(FILE *fp, uint32_t *encoded, size_t encoded_size)
{
const struct isa_decode_options opts = {
.show_errors = true,
.branch_labels = true,
.cbdata = fp,
.pre_instr_cb = disasm_instr_cb,
};
isa_disasm(encoded, encoded_size, fp, &opts);
}

108
src/nouveau/mme/mme_tu104.c
View File

@@ -3,9 +3,8 @@
* SPDX-License-Identifier: MIT
*/
#include "mme_tu104.h"
#include "mme_tu104_encode.h"
#include "util/u_math.h"
#include "mme_bitpack_helpers.h"
#include <stdlib.h>
@@ -88,68 +87,70 @@ mme_tu104_encode(uint32_t *out, uint32_t inst_count,
const struct mme_tu104_inst *insts)
{
for (uint32_t i = 0; i < inst_count; i++) {
bitmask_t enc = encode__instruction(NULL, NULL, insts[i]);
uint32_t b[3] = { 0, 0, 0};
pack_uint(b, 0, 0, insts[i].end_next);
pack_uint(b, 1, 4, insts[i].pred_mode);
pack_uint(b, 5, 9, insts[i].pred);
pack_uint(b, 10, 14, insts[i].alu[0].op);
pack_uint(b, 15, 19, insts[i].alu[0].dst);
pack_uint(b, 20, 24, insts[i].alu[0].src[0]);
pack_uint(b, 25, 29, insts[i].alu[0].src[1]);
pack_uint(b, 30, 45, insts[i].imm[0]);
pack_uint(b, 46, 50, insts[i].alu[1].op);
pack_uint(b, 51, 55, insts[i].alu[1].dst);
pack_uint(b, 56, 60, insts[i].alu[1].src[0]);
pack_uint(b, 61, 65, insts[i].alu[1].src[1]);
pack_uint(b, 66, 81, insts[i].imm[1]);
pack_uint(b, 82, 84, insts[i].out[0].mthd);
pack_uint(b, 85, 88, insts[i].out[0].emit);
pack_uint(b, 89, 91, insts[i].out[1].mthd);
pack_uint(b, 92, 95, insts[i].out[1].emit);
/* Annoyingly, the words are reversed in the actual encoding */
out[i * 3 + 0] = enc.bitset[2];
out[i * 3 + 1] = enc.bitset[1];
out[i * 3 + 2] = enc.bitset[0];
out[i * 3 + 2] = b[0];
out[i * 3 + 1] = b[1];
out[i * 3 + 0] = b[2];
}
}
static uint64_t
unpack_field(bitmask_t bitmask, unsigned low, unsigned high, bool is_signed)
{
bitmask_t field, mask;
assert(high >= low);
BITSET_ZERO(mask.bitset);
BITSET_SET_RANGE(mask.bitset, 0, high - low);
BITSET_COPY(field.bitset, bitmask.bitset);
BITSET_SHR(field.bitset, low);
BITSET_AND(field.bitset, field.bitset, mask.bitset);
uint64_t data = bitmask_to_uint64_t(field);
if (is_signed)
data = util_sign_extend(data, high - low + 1);
return data;
}
void
mme_tu104_decode(struct mme_tu104_inst *insts,
const uint32_t *in, uint32_t inst_count)
{
for (uint32_t i = 0; i < inst_count; i++) {
/* Annoyingly, the words are reversed in the actual encoding */
bitmask_t enc;
enc.bitset[0] = in[i * 3 + 2];
enc.bitset[1] = in[i * 3 + 1];
enc.bitset[2] = in[i * 3 + 0];
const uint32_t b[3] = {
in[i * 3 + 2],
in[i * 3 + 1],
in[i * 3 + 0],
};
insts[i].end_next = unpack_field(enc, 0, 0, false);
insts[i].pred_mode = unpack_field(enc, 1, 4, false);
insts[i].pred = unpack_field(enc, 5, 9, false);
insts[i].end_next = unpack_uint(b, 0, 0);
insts[i].pred_mode = unpack_uint(b, 1, 4);
insts[i].pred = unpack_uint(b, 5, 9);
insts[i].alu[0].op = unpack_field(enc, 10, 14, false);
insts[i].alu[0].dst = unpack_field(enc, 15, 19, false);
insts[i].alu[0].src[0] = unpack_field(enc, 20, 24, false);
insts[i].alu[0].src[1] = unpack_field(enc, 25, 29, false);
insts[i].imm[0] = unpack_field(enc, 30, 45, false);
insts[i].alu[0].op = unpack_uint(b, 10, 14);
insts[i].alu[0].dst = unpack_uint(b, 15, 19);
insts[i].alu[0].src[0] = unpack_uint(b, 20, 24);
insts[i].alu[0].src[1] = unpack_uint(b, 25, 29);
insts[i].imm[0] = unpack_uint(b, 30, 45);
insts[i].alu[1].op = unpack_field(enc, 46, 50, false);
insts[i].alu[1].dst = unpack_field(enc, 51, 55, false);
insts[i].alu[1].src[0] = unpack_field(enc, 56, 60, false);
insts[i].alu[1].src[1] = unpack_field(enc, 61, 65, false);
insts[i].imm[1] = unpack_field(enc, 66, 81, false);
insts[i].alu[1].op = unpack_uint(b, 46, 50);
insts[i].alu[1].dst = unpack_uint(b, 51, 55);
insts[i].alu[1].src[0] = unpack_uint(b, 56, 60);
insts[i].alu[1].src[1] = unpack_uint(b, 61, 65);
insts[i].imm[1] = unpack_uint(b, 66, 81);
insts[i].out[0].mthd = unpack_field(enc, 82, 84, false);
insts[i].out[0].emit = unpack_field(enc, 85, 88, false);
insts[i].out[0].mthd = unpack_uint(b, 82, 84);
insts[i].out[0].emit = unpack_uint(b, 85, 88);
insts[i].out[1].mthd = unpack_field(enc, 89, 91, false);
insts[i].out[1].emit = unpack_field(enc, 92, 95, false);
insts[i].out[1].mthd = unpack_uint(b, 89, 91);
insts[i].out[1].emit = unpack_uint(b, 92, 95);
}
}
@@ -552,3 +553,14 @@ mme_tu104_print(FILE *fp, const struct mme_tu104_inst *insts,
mme_tu104_print_inst(fp, 1, &insts[i]);
}
}
void
mme_tu104_dump(FILE *fp, uint32_t *encoded, size_t encoded_size)
{
uint32_t inst_count = encoded_size / 12;
for (uint32_t i = 0; i < inst_count; i++) {
struct mme_tu104_inst inst;
mme_tu104_decode(&inst, &encoded[i * 3], 1);
mme_tu104_print_inst(fp, 1, &inst);
}
}

161
src/nouveau/mme/mme_tu104.xml
View File

@@ -1,161 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<!--
Copyright © 2022 Collabora Ltd.
SPDX-License-Identifier: MIT
-->
<isa>
<enum name="#pred">
<value val="0" display="UUUU"/>
<value val="1" display="TTTT"/>
<value val="2" display="FFFF"/>
<value val="3" display="TTUU"/>
<value val="4" display="FFUU"/>
<value val="5" display="TFUU"/>
<value val="6" display="TUUU"/>
<value val="7" display="FUUU"/>
<value val="8" display="UUTT"/>
<value val="9" display="UUTF"/>
<value val="10" display="UUTU"/>
<value val="11" display="UUFT"/>
<value val="12" display="UUFF"/>
<value val="13" display="UUFU"/>
<value val="14" display="UUUT"/>
<value val="15" display="UUUF"/>
</enum>
<enum name="#reg">
<value val="0" display="r0"/>
<value val="1" display="r1"/>
<value val="2" display="r2"/>
<value val="3" display="r3"/>
<value val="4" display="r4"/>
<value val="5" display="r5"/>
<value val="6" display="r6"/>
<value val="7" display="r7"/>
<value val="8" display="r8"/>
<value val="9" display="r9"/>
<value val="10" display="r10"/>
<value val="11" display="r11"/>
<value val="12" display="r12"/>
<value val="13" display="r13"/>
<value val="14" display="r14"/>
<value val="15" display="r15"/>
<value val="16" display="r16"/>
<value val="17" display="r17"/>
<value val="18" display="r18"/>
<value val="19" display="r19"/>
<value val="20" display="r20"/>
<value val="21" display="r21"/>
<value val="22" display="r22"/>
<value val="23" display="r23"/>
<value val="24" display="zero"/>
<value val="25" display="imm"/>
<value val="26" display="immpair"/>
<value val="27" display="imm32"/>
<value val="28" display="load0"/>
<value val="29" display="load1"/>
</enum>
<enum name="#alu-op">
<value val="0" display="ADD"/>
<value val="1" display="ADDC"/>
<value val="2" display="SUB"/>
<value val="3" display="SUBB"/>
<value val="4" display="MUL"/>
<value val="5" display="MULH"/>
<value val="6" display="MULU"/>
<value val="7" display="EXTENDED"/>
<value val="8" display="CLZ"/>
<value val="9" display="SLL"/>
<value val="10" display="SRL"/>
<value val="11" display="SRA"/>
<value val="12" display="AND"/>
<value val="13" display="NAND"/>
<value val="14" display="OR"/>
<value val="15" display="XOR"/>
<value val="16" display="MERGE"/>
<value val="17" display="SLT"/>
<value val="18" display="SLTU"/>
<value val="19" display="SLE"/>
<value val="20" display="SLEU"/>
<value val="21" display="SEQ"/>
<value val="22" display="STATE"/>
<value val="23" display="LOOP"/>
<value val="24" display="JAL"/>
<value val="25" display="BLT"/>
<value val="26" display="BLTU"/>
<value val="27" display="BLE"/>
<value val="28" display="BLEU"/>
<value val="29" display="BEQ"/>
<value val="30" display="DREAD"/>
<value val="31" display="DWRITE"/>
</enum>
<enum name="#out-op">
<value val="0" display="none"/>
<value val="1" display="alu0"/>
<value val="2" display="alu1"/>
<value val="3" display="load0"/>
<value val="4" display="load1"/>
<value val="5" display="imm0"/>
<value val="6" display="imm1"/>
<!-- val="7" display="reserved" -->
<value val="8" display="immhigh0"/>
<value val="9" display="immhigh1"/>
<value val="10" display="imm32"/>
</enum>
<bitset name="#alu" size="20">
<display>
{DST} = {OP} {SRC0} {SRC1}
</display>
<field name="OP" low="0" high="4" type="#alu-op"/>
<field name="DST" low="5" high="9" type="#reg"/>
<field name="SRC0" low="10" high="14" type="#reg"/>
<field name="SRC1" low="15" high="19" type="#reg"/>
<encode type="struct mme_tu104_alu">
<map name="DST">src.dst</map>
<map name="OP">src.op</map>
<map name="SRC0">src.src[0]</map>
<map name="SRC1">src.src[1]</map>
</encode>
</bitset>
<bitset name="#out" size="7">
<display>
{EMIT} -> {MTHD}
</display>
<field name="MTHD" low="0" high="2" type="#out-op"/>
<field name="EMIT" low="3" high="6" type="#out-op"/>
<encode type="struct mme_tu104_out">
<map name="MTHD">src.mthd</map>
<map name="EMIT">src.emit</map>
</encode>
</bitset>
<bitset name="#instruction" size="96">
<display>
{END_NEXT}({PRED} {PRED_MODE}) imm=[{IMM0}, {IMM1}], {ALU0}, {ALU1}, {OUT0}, {OUT1}
</display>
<field name="END_NEXT" pos="0" type="bool" display="(end-next)"/>
<field name="PRED_MODE" low="1" high="4" type="#pred"/>
<field name="PRED" low="5" high="9" type="#reg"/>
<field name="ALU0" low="10" high="29" type="#alu"/>
<field name="IMM0" low="30" high="45" type="uint"/>
<field name="ALU1" low="46" high="65" type="#alu"/>
<field name="IMM1" low="66" high="81" type="uint"/>
<field name="OUT0" low="82" high="88" type="#out"/>
<field name="OUT1" low="89" high="95" type="#out"/>
<encode type="struct mme_tu104_inst">
<map name="END_NEXT">src.end_next</map>
<map name="PRED_MODE">src.pred_mode</map>
<map name="PRED">src.pred</map>
<map name="ALU0">src.alu[0]</map>
<map name="IMM0">src.imm[0]</map>
<map name="ALU1">src.alu[1]</map>
<map name="IMM1">src.imm[1]</map>
<map name="OUT0">src.out[0]</map>
<map name="OUT1">src.out[1]</map>
</encode>
</bitset>
</isa>

40
src/nouveau/mme/mme_tu104_dump.c
View File

@@ -1,40 +0,0 @@
/*
* Copyright © 2022 Collabora Ltd.
* SPDX-License-Identifier: MIT
*/
#include "mme_tu104.h"
#include "mme_tu104_isa.h"
#include "isa.h"
#include <stdlib.h>
static void
disasm_instr_cb(void *d, unsigned n, void *instr)
{
uint32_t *dwords = (uint32_t *)instr;
fprintf(d, "%3d[%08x_%08x_%08x] ", n, dwords[2], dwords[1], dwords[0]);
}
void
mme_tu104_dump(FILE *fp, uint32_t *encoded, size_t encoded_size)
{
assert(encoded_size % 12 == 0);
uint32_t *swapped = malloc(encoded_size);
for (uint32_t i = 0; i < (encoded_size / 12); i++) {
swapped[i * 3 + 0] = encoded[i * 3 + 2];
swapped[i * 3 + 1] = encoded[i * 3 + 1];
swapped[i * 3 + 2] = encoded[i * 3 + 0];
}
const struct isa_decode_options opts = {
.show_errors = true,
.branch_labels = true,
.cbdata = fp,
.pre_instr_cb = disasm_instr_cb,
};
isa_disasm(swapped, encoded_size, fp, &opts);
free(swapped);
}