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anv: Use pending pipe control mechanism in flush_pipeline_select()

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This removes the repeated implementation of a workaround and a
per-platform case.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14301>
This commit is contained in:
Caio Oliveira
2021-12-23 23:17:28 -08:00
committed by Marge Bot
parent 9ba7bc17d3
commit 313aeee84b
1 changed files with 14 additions and 27 deletions
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41
src/intel/vulkan/genX_cmd_buffer.c
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@@ -5443,34 +5443,21 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
* stalling PIPE_CONTROL command followed by another PIPE_CONTROL * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
* command to invalidate read only caches prior to programming * command to invalidate read only caches prior to programming
* MI_PIPELINE_SELECT command to change the Pipeline Select Mode. * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
*
* Note the cmd_buffer_apply_pipe_flushes will split this into two
* PIPE_CONTROLs.
*/ */
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { anv_add_pending_pipe_bits(cmd_buffer,
pc.RenderTargetCacheFlushEnable = true; ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
pc.DepthCacheFlushEnable = true; ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
#if GFX_VER >= 12 ANV_PIPE_HDC_PIPELINE_FLUSH_BIT |
pc.HDCPipelineFlushEnable = true; ANV_PIPE_CS_STALL_BIT |
#else ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
pc.DCFlushEnable = true; ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT |
#endif ANV_PIPE_STATE_CACHE_INVALIDATE_BIT |
pc.PostSyncOperation = NoWrite; ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT,
pc.CommandStreamerStallEnable = true; "flush and invalidate for PIPELINE_SELECT");
#if GFX_VER >= 12 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
/* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must be
* set with any PIPE_CONTROL with Depth Flush Enable bit set.
*/
pc.DepthStallEnable = true;
#endif
anv_debug_dump_pc(pc);
}
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.TextureCacheInvalidationEnable = true;
pc.ConstantCacheInvalidationEnable = true;
pc.StateCacheInvalidationEnable = true;
pc.InstructionCacheInvalidateEnable = true;
pc.PostSyncOperation = NoWrite;
anv_debug_dump_pc(pc);
}
anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT), ps) { anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT), ps) {
#if GFX_VER >= 9 #if GFX_VER >= 9