anv: Use pending pipe control mechanism in flush_pipeline_select()
This removes the repeated implementation of a workaround and a per-platform case. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14301>
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@@ -5443,34 +5443,21 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
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* stalling PIPE_CONTROL command followed by another PIPE_CONTROL
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* command to invalidate read only caches prior to programming
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* MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
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*
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* Note the cmd_buffer_apply_pipe_flushes will split this into two
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* PIPE_CONTROLs.
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*/
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
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pc.RenderTargetCacheFlushEnable = true;
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pc.DepthCacheFlushEnable = true;
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#if GFX_VER >= 12
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pc.HDCPipelineFlushEnable = true;
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#else
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pc.DCFlushEnable = true;
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#endif
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pc.PostSyncOperation = NoWrite;
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pc.CommandStreamerStallEnable = true;
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#if GFX_VER >= 12
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/* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must be
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* set with any PIPE_CONTROL with Depth Flush Enable bit set.
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*/
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pc.DepthStallEnable = true;
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#endif
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anv_debug_dump_pc(pc);
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}
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
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pc.TextureCacheInvalidationEnable = true;
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pc.ConstantCacheInvalidationEnable = true;
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pc.StateCacheInvalidationEnable = true;
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pc.InstructionCacheInvalidateEnable = true;
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pc.PostSyncOperation = NoWrite;
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anv_debug_dump_pc(pc);
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}
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anv_add_pending_pipe_bits(cmd_buffer,
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ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
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ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
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ANV_PIPE_HDC_PIPELINE_FLUSH_BIT |
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ANV_PIPE_CS_STALL_BIT |
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ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
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ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT |
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ANV_PIPE_STATE_CACHE_INVALIDATE_BIT |
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ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT,
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"flush and invalidate for PIPELINE_SELECT");
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genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT), ps) {
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#if GFX_VER >= 9
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