nir: add the core datastructures
This includes all the instructions, ifs, loops, functions, etc. This is similar to the information in ir.h. v2: Jason Ekstrand <jason.ekstrand@intel.com>: Include ralloc and hash_table from the util directory whitespace fixes Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-By glenn.kennard <glenn.kennard@gmail.com>
This commit is contained in:
Connor Abbott
committed by
Jason Ekstrand
Jason Ekstrand
parent
b5ca34a211
commit
30c4678f64
@@ -14,6 +14,8 @@ LIBGLCPP_GENERATED_FILES = \
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$(GLSL_BUILDDIR)/glcpp/glcpp-parse.c
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NIR_FILES = \
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$(GLSL_SRCDIR)/nir/nir_intrinsics.c \
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$(GLSL_SRCDIR)/nir/nir_opcodes.c \
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$(GLSL_SRCDIR)/nir/nir_types.cpp
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# libglsl
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1150
src/glsl/nir/nir.h
Normal file
1150
src/glsl/nir/nir.h
Normal file
File diff suppressed because it is too large
Load Diff
49
src/glsl/nir/nir_intrinsics.c
Normal file
49
src/glsl/nir/nir_intrinsics.c
Normal file
@@ -0,0 +1,49 @@
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/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Connor Abbott (cwabbott0@gmail.com)
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*
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*/
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#include "nir.h"
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#define OPCODE(name) nir_intrinsic_##name
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#define INTRINSIC(_name, _num_srcs, _src_components, _has_dest, \
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_dest_components, _num_variables, _num_indices, _flags) \
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{ \
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.name = #_name, \
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.num_srcs = _num_srcs, \
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.src_components = _src_components, \
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.has_dest = _has_dest, \
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.dest_components = _dest_components, \
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.num_variables = _num_variables, \
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.num_indices = _num_indices, \
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.flags = _flags \
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},
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#define LAST_INTRINSIC(name)
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const nir_intrinsic_info nir_intrinsic_infos[nir_num_intrinsics] = {
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#include "nir_intrinsics.h"
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};
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158
src/glsl/nir/nir_intrinsics.h
Normal file
158
src/glsl/nir/nir_intrinsics.h
Normal file
@@ -0,0 +1,158 @@
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/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Connor Abbott (cwabbott0@gmail.com)
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*
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*/
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/**
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* This header file defines all the available intrinsics in one place. It
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* expands to a list of macros of the form:
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*
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* INTRINSIC(name, num_srcs, src_components, has_dest, dest_components,
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* num_variables, num_indices, flags)
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*
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* Which should correspond one-to-one with the nir_intrinsic_info structure. It
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* is included in both ir.h to create the nir_intrinsic enum (with members of
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* the form nir_intrinsic_(name)) and and in opcodes.c to create
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* nir_intrinsic_infos, which is a const array of nir_intrinsic_info structures
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* for each intrinsic.
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*/
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#define ARR(...) { __VA_ARGS__ }
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INTRINSIC(load_var_vec1, 0, ARR(), true, 1, 1, 0,
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NIR_INTRINSIC_CAN_ELIMINATE)
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INTRINSIC(load_var_vec2, 0, ARR(), true, 2, 1, 0,
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NIR_INTRINSIC_CAN_ELIMINATE)
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INTRINSIC(load_var_vec3, 0, ARR(), true, 3, 1, 0,
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NIR_INTRINSIC_CAN_ELIMINATE)
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INTRINSIC(load_var_vec4, 0, ARR(), true, 4, 1, 0,
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NIR_INTRINSIC_CAN_ELIMINATE)
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INTRINSIC(store_var_vec1, 1, ARR(1), false, 0, 1, 0, 0)
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INTRINSIC(store_var_vec2, 1, ARR(2), false, 0, 1, 0, 0)
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INTRINSIC(store_var_vec3, 1, ARR(3), false, 0, 1, 0, 0)
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INTRINSIC(store_var_vec4, 1, ARR(4), false, 0, 1, 0, 0)
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INTRINSIC(copy_var, 0, ARR(), false, 0, 2, 0, 0)
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/*
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* a barrier is an intrinsic with no inputs/outputs but which can't be moved
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* around/optimized in general
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*/
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#define BARRIER(name) INTRINSIC(name, 0, ARR(), false, 0, 0, 0, 0)
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BARRIER(discard)
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INTRINSIC(emit_vertex, 0, ARR(), false, 0, 0, 1, 0)
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INTRINSIC(end_primitive, 0, ARR(), false, 0, 0, 1, 0)
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/*
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* Atomic counters
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*
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* The *_var variants take an atomic_uint nir_variable, while the other,
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* lowered, variants take a constant buffer index and register offset.
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*/
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#define ATOMIC(name, flags) \
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INTRINSIC(atomic_counter_##name##_var, 0, ARR(), true, 1, 1, 0, flags) \
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INTRINSIC(atomic_counter_##name, 1, ARR(1), true, 1, 0, 1, flags)
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ATOMIC(inc, 0)
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ATOMIC(dec, 0)
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ATOMIC(read, NIR_INTRINSIC_CAN_ELIMINATE)
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#define SYSTEM_VALUE(name, components) \
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INTRINSIC(load_##name, 0, ARR(), true, components, 0, 0, \
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NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
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SYSTEM_VALUE(front_face, 1)
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SYSTEM_VALUE(vertex_id, 1)
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SYSTEM_VALUE(instance_id, 1)
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SYSTEM_VALUE(sample_id, 1)
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SYSTEM_VALUE(sample_pos, 2)
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SYSTEM_VALUE(sample_mask_in, 1)
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SYSTEM_VALUE(invocation_id, 1)
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#define LOAD(name, num_indices, flags) \
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INTRINSIC(load_##name##_vec1, 0, ARR(), true, 1, 0, num_indices, \
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NIR_INTRINSIC_CAN_ELIMINATE | flags) \
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INTRINSIC(load_##name##_vec2, 0, ARR(), true, 2, 0, num_indices, \
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NIR_INTRINSIC_CAN_ELIMINATE | flags) \
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INTRINSIC(load_##name##_vec3, 0, ARR(), true, 3, 0, num_indices, \
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NIR_INTRINSIC_CAN_ELIMINATE | flags) \
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INTRINSIC(load_##name##_vec4, 0, ARR(), true, 4, 0, num_indices, \
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NIR_INTRINSIC_CAN_ELIMINATE | flags) \
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INTRINSIC(load_##name##_vec1_indirect, 1, ARR(1), true, 1, 0, num_indices, \
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NIR_INTRINSIC_CAN_ELIMINATE | flags) \
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INTRINSIC(load_##name##_vec2_indirect, 1, ARR(1), true, 2, 0, num_indices, \
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NIR_INTRINSIC_CAN_ELIMINATE | flags) \
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INTRINSIC(load_##name##_vec3_indirect, 1, ARR(1), true, 3, 0, num_indices, \
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NIR_INTRINSIC_CAN_ELIMINATE | flags) \
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INTRINSIC(load_##name##_vec4_indirect, 1, ARR(1), true, 4, 0, num_indices, \
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NIR_INTRINSIC_CAN_ELIMINATE | flags) \
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/*
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* The first index is the address to load from, and the second index is the
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* number of array elements to load. For UBO's (and SSBO's), the first index
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* is the UBO buffer index (TODO nonconstant UBO buffer index) and the second
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* and third indices play the role of the first and second indices in the other
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* loads. Indirect loads have an additional register input, which is added
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* to the constant address to compute the final address to load from.
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*
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* For vector backends, the address is in terms of one vec4, and so each array
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* element is +4 scalar components from the previous array element. For scalar
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* backends, the address is in terms of a single 4-byte float/int and arrays
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* elements begin immediately after the previous array element.
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*/
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LOAD(uniform, 2, NIR_INTRINSIC_CAN_REORDER)
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LOAD(ubo, 3, NIR_INTRINSIC_CAN_REORDER)
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LOAD(input, 2, NIR_INTRINSIC_CAN_REORDER)
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/* LOAD(ssbo, 2, 0) */
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#define STORE(name, num_indices, flags) \
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INTRINSIC(store_##name##_vec1, 1, ARR(1), false, 0, 0, num_indices, flags) \
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INTRINSIC(store_##name##_vec2, 1, ARR(2), false, 0, 0, num_indices, flags) \
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INTRINSIC(store_##name##_vec3, 1, ARR(3), false, 0, 0, num_indices, flags) \
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INTRINSIC(store_##name##_vec4, 1, ARR(4), false, 0, 0, num_indices, flags) \
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INTRINSIC(store_##name##_vec1_indirect, 2, ARR(1, 1), false, 0, 0, \
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num_indices, flags) \
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INTRINSIC(store_##name##_vec2_indirect, 2, ARR(2, 1), false, 0, 0, \
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num_indices, flags) \
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INTRINSIC(store_##name##_vec3_indirect, 2, ARR(3, 1), false, 0, 0, \
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num_indices, flags) \
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INTRINSIC(store_##name##_vec4_indirect, 2, ARR(4, 1), false, 0, 0, \
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num_indices, flags) \
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/*
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* Stores work the same way as loads, except now the first register input is
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* the value or array to store and the optional second input is the indirect
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* offset.
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*/
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STORE(output, 2, 0)
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/* STORE(ssbo, 3, 0) */
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LAST_INTRINSIC(store_output_vec4_indirect)
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46
src/glsl/nir/nir_opcodes.c
Normal file
46
src/glsl/nir/nir_opcodes.c
Normal file
@@ -0,0 +1,46 @@
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/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Connor Abbott (cwabbott0@gmail.com)
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*
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*/
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#include "nir.h"
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#define OPCODE(_name, _num_inputs, _per_component, _output_size, _output_type, \
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_input_sizes, _input_types) \
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{ \
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.name = #_name, \
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.num_inputs = _num_inputs, \
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.per_component = _per_component, \
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.output_size = _output_size, \
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.output_type = _output_type, \
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.input_sizes = _input_sizes, \
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.input_types = _input_types, \
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},
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#define LAST_OPCODE(name)
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const nir_op_info nir_op_infos[nir_num_opcodes] = {
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#include "nir_opcodes.h"
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};
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346
src/glsl/nir/nir_opcodes.h
Normal file
346
src/glsl/nir/nir_opcodes.h
Normal file
@@ -0,0 +1,346 @@
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/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Connor Abbott (cwabbott0@gmail.com)
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*
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*/
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/**
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* This header file defines all the available opcodes in one place. It expands
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* to a list of macros of the form:
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*
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* OPCODE(name, num_inputs, per_component, output_size, output_type,
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* input_sizes, input_types)
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*
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* Which should correspond one-to-one with the nir_op_info structure. It is
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* included in both ir.h to create the nir_op enum (with members of the form
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* nir_op_(name)) and and in opcodes.c to create nir_op_infos, which is a
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* const array of nir_op_info structures for each opcode.
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*/
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#define ARR(...) { __VA_ARGS__ }
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#define UNOP(name, type) OPCODE(name, 1, false, 0, type, ARR(0), ARR(type))
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#define UNOP_CONVERT(name, in_type, out_type) \
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OPCODE(name, 1, false, 0, out_type, ARR(0), ARR(in_type))
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#define UNOP_HORIZ(name, output_size, output_type, input_size, input_type) \
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OPCODE(name, 1, true, output_size, output_type, ARR(input_size), \
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ARR(input_type))
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#define UNOP_REDUCE(name, output_size, output_type, input_type) \
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UNOP_HORIZ(name##2, output_size, output_type, 2, input_type) \
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UNOP_HORIZ(name##3, output_size, output_type, 3, input_type) \
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UNOP_HORIZ(name##4, output_size, output_type, 4, input_type)
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/**
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* These two move instructions differ in what modifiers they support and what
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* the negate modifier means. Otherwise, they are identical.
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*/
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UNOP(fmov, nir_type_float)
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UNOP(imov, nir_type_int)
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UNOP(inot, nir_type_int) /* invert every bit of the integer */
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UNOP(fnot, nir_type_float) /* (src == 0.0) ? 1.0 : 0.0 */
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UNOP(fsign, nir_type_float)
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UNOP(isign, nir_type_int)
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UNOP(frcp, nir_type_float)
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UNOP(frsq, nir_type_float)
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UNOP(fsqrt, nir_type_float)
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UNOP(fexp, nir_type_float) /* < e^x */
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UNOP(flog, nir_type_float) /* log base e */
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UNOP(fexp2, nir_type_float)
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UNOP(flog2, nir_type_float)
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UNOP_CONVERT(f2i, nir_type_float, nir_type_int) /**< Float-to-integer conversion. */
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UNOP_CONVERT(f2u, nir_type_float, nir_type_unsigned) /**< Float-to-unsigned conversion. */
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UNOP_CONVERT(i2f, nir_type_int, nir_type_float) /**< Integer-to-float conversion. */
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UNOP_CONVERT(f2b, nir_type_float, nir_type_bool) /**< Float-to-boolean conversion */
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UNOP_CONVERT(b2f, nir_type_bool, nir_type_float) /**< Boolean-to-float conversion */
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UNOP_CONVERT(i2b, nir_type_int, nir_type_bool) /**< int-to-boolean conversion */
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UNOP_CONVERT(b2i, nir_type_bool, nir_type_int) /**< Boolean-to-int conversion */
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UNOP_CONVERT(u2f, nir_type_unsigned, nir_type_float) /**< Unsigned-to-float conversion. */
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UNOP_REDUCE(bany, 1, nir_type_bool, nir_type_bool) /* returns ~0 if any component of src[0] != 0 */
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UNOP_REDUCE(ball, 1, nir_type_bool, nir_type_bool) /* returns ~0 if all components of src[0] != 0 */
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UNOP_REDUCE(fany, 1, nir_type_float, nir_type_float) /* returns 1.0 if any component of src[0] != 0 */
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UNOP_REDUCE(fall, 1, nir_type_float, nir_type_float) /* returns 1.0 if all components of src[0] != 0 */
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/**
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* \name Unary floating-point rounding operations.
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*/
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/*@{*/
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UNOP(ftrunc, nir_type_float)
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UNOP(fceil, nir_type_float)
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UNOP(ffloor, nir_type_float)
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UNOP(ffract, nir_type_float)
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UNOP(fround_even, nir_type_float)
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/*@}*/
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/**
|
||||
* \name Trigonometric operations.
|
||||
*/
|
||||
/*@{*/
|
||||
UNOP(fsin, nir_type_float)
|
||||
UNOP(fcos, nir_type_float)
|
||||
UNOP(fsin_reduced, nir_type_float)
|
||||
UNOP(fcos_reduced, nir_type_float)
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* \name Partial derivatives.
|
||||
*/
|
||||
/*@{*/
|
||||
UNOP(fddx, nir_type_float)
|
||||
UNOP(fddy, nir_type_float)
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* \name Floating point pack and unpack operations.
|
||||
*/
|
||||
/*@{*/
|
||||
UNOP_HORIZ(pack_snorm_2x16, 1, nir_type_unsigned, 2, nir_type_float)
|
||||
UNOP_HORIZ(pack_snorm_4x8, 1, nir_type_unsigned, 4, nir_type_float)
|
||||
UNOP_HORIZ(pack_unorm_2x16, 1, nir_type_unsigned, 2, nir_type_float)
|
||||
UNOP_HORIZ(pack_unorm_4x8, 1, nir_type_unsigned, 4, nir_type_float)
|
||||
UNOP_HORIZ(pack_half_2x16, 1, nir_type_unsigned, 2, nir_type_float)
|
||||
UNOP_HORIZ(unpack_snorm_2x16, 2, nir_type_float, 1, nir_type_unsigned)
|
||||
UNOP_HORIZ(unpack_snorm_4x8, 4, nir_type_float, 1, nir_type_unsigned)
|
||||
UNOP_HORIZ(unpack_unorm_2x16, 2, nir_type_float, 1, nir_type_unsigned)
|
||||
UNOP_HORIZ(unpack_unorm_4x8, 4, nir_type_float, 1, nir_type_unsigned)
|
||||
UNOP_HORIZ(unpack_half_2x16, 2, nir_type_float, 1, nir_type_unsigned)
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* \name Lowered floating point unpacking operations.
|
||||
*/
|
||||
/*@{*/
|
||||
UNOP_HORIZ(unpack_half_2x16_split_x, 1, nir_type_float, 1, nir_type_unsigned)
|
||||
UNOP_HORIZ(unpack_half_2x16_split_y, 1, nir_type_float, 1, nir_type_unsigned)
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* \name Bit operations, part of ARB_gpu_shader5.
|
||||
*/
|
||||
/*@{*/
|
||||
UNOP(bitfield_reverse, nir_type_unsigned)
|
||||
UNOP(bit_count, nir_type_unsigned)
|
||||
UNOP(find_msb, nir_type_unsigned)
|
||||
UNOP(find_lsb, nir_type_unsigned)
|
||||
/*@}*/
|
||||
|
||||
UNOP_HORIZ(fnoise1_1, 1, nir_type_float, 1, nir_type_float)
|
||||
UNOP_HORIZ(fnoise1_2, 1, nir_type_float, 2, nir_type_float)
|
||||
UNOP_HORIZ(fnoise1_3, 1, nir_type_float, 3, nir_type_float)
|
||||
UNOP_HORIZ(fnoise1_4, 1, nir_type_float, 4, nir_type_float)
|
||||
UNOP_HORIZ(fnoise2_1, 2, nir_type_float, 1, nir_type_float)
|
||||
UNOP_HORIZ(fnoise2_2, 2, nir_type_float, 2, nir_type_float)
|
||||
UNOP_HORIZ(fnoise2_3, 2, nir_type_float, 3, nir_type_float)
|
||||
UNOP_HORIZ(fnoise2_4, 2, nir_type_float, 4, nir_type_float)
|
||||
UNOP_HORIZ(fnoise3_1, 3, nir_type_float, 1, nir_type_float)
|
||||
UNOP_HORIZ(fnoise3_2, 3, nir_type_float, 2, nir_type_float)
|
||||
UNOP_HORIZ(fnoise3_3, 3, nir_type_float, 3, nir_type_float)
|
||||
UNOP_HORIZ(fnoise3_4, 3, nir_type_float, 4, nir_type_float)
|
||||
UNOP_HORIZ(fnoise4_1, 4, nir_type_float, 1, nir_type_float)
|
||||
UNOP_HORIZ(fnoise4_2, 4, nir_type_float, 2, nir_type_float)
|
||||
UNOP_HORIZ(fnoise4_3, 4, nir_type_float, 3, nir_type_float)
|
||||
UNOP_HORIZ(fnoise4_4, 4, nir_type_float, 4, nir_type_float)
|
||||
|
||||
#define BINOP(name, type) \
|
||||
OPCODE(name, 2, true, 0, type, ARR(0, 0), ARR(type, type))
|
||||
#define BINOP_CONVERT(name, out_type, in_type) \
|
||||
OPCODE(name, 2, true, 0, out_type, ARR(0, 0), ARR(in_type, in_type))
|
||||
#define BINOP_COMPARE(name, type) BINOP_CONVERT(name, nir_type_bool, type)
|
||||
#define BINOP_HORIZ(name, output_size, output_type, src1_size, src1_type, \
|
||||
src2_size, src2_type) \
|
||||
OPCODE(name, 2, true, output_size, output_type, ARR(src1_size, src2_size), \
|
||||
ARR(src1_type, src2_type))
|
||||
#define BINOP_REDUCE(name, output_size, output_type, src_type) \
|
||||
BINOP_HORIZ(name##2, output_size, output_type, 2, src_type, 2, src_type) \
|
||||
BINOP_HORIZ(name##3, output_size, output_type, 3, src_type, 3, src_type) \
|
||||
BINOP_HORIZ(name##4, output_size, output_type, 4, src_type, 4, src_type) \
|
||||
|
||||
BINOP(fadd, nir_type_float)
|
||||
BINOP(iadd, nir_type_int)
|
||||
BINOP(fsub, nir_type_float)
|
||||
BINOP(isub, nir_type_int)
|
||||
|
||||
BINOP(fmul, nir_type_float)
|
||||
BINOP(imul, nir_type_int) /* low 32-bits of signed/unsigned integer multiply */
|
||||
BINOP(imul_high, nir_type_int) /* high 32-bits of signed integer multiply */
|
||||
BINOP(umul_high, nir_type_int) /* high 32-bits of unsigned integer multiply */
|
||||
|
||||
BINOP(fdiv, nir_type_float)
|
||||
BINOP(idiv, nir_type_int)
|
||||
BINOP(udiv, nir_type_unsigned)
|
||||
|
||||
/**
|
||||
* returns a boolean representing the carry resulting from the addition of
|
||||
* the two unsigned arguments.
|
||||
*/
|
||||
BINOP_CONVERT(uadd_carry, nir_type_bool, nir_type_unsigned)
|
||||
|
||||
/**
|
||||
* returns a boolean representing the borrow resulting from the subtraction
|
||||
* of the two unsigned arguments.
|
||||
*/
|
||||
BINOP_CONVERT(usub_borrow, nir_type_bool, nir_type_unsigned)
|
||||
|
||||
BINOP(fmod, nir_type_float)
|
||||
BINOP(umod, nir_type_unsigned)
|
||||
|
||||
/**
|
||||
* \name comparisons
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/**
|
||||
* these integer-aware comparisons return a boolean (0 or ~0)
|
||||
*/
|
||||
BINOP_COMPARE(flt, nir_type_float)
|
||||
BINOP_COMPARE(fge, nir_type_float)
|
||||
BINOP_COMPARE(feq, nir_type_float)
|
||||
BINOP_COMPARE(fne, nir_type_float)
|
||||
BINOP_COMPARE(ilt, nir_type_int)
|
||||
BINOP_COMPARE(ige, nir_type_int)
|
||||
BINOP_COMPARE(ieq, nir_type_int)
|
||||
BINOP_COMPARE(ine, nir_type_int)
|
||||
BINOP_COMPARE(ult, nir_type_int)
|
||||
BINOP_COMPARE(uge, nir_type_int)
|
||||
|
||||
/** integer-aware GLSL-style comparisons that compare floats and ints */
|
||||
BINOP_REDUCE(ball_fequal, 1, nir_type_bool, nir_type_float)
|
||||
BINOP_REDUCE(bany_fnequal, 1, nir_type_bool, nir_type_float)
|
||||
BINOP_REDUCE(ball_iequal, 1, nir_type_bool, nir_type_int)
|
||||
BINOP_REDUCE(bany_inequal, 1, nir_type_bool, nir_type_int)
|
||||
|
||||
/** non-integer-aware GLSL-style comparisons that return 0.0 or 1.0 */
|
||||
BINOP_REDUCE(fall_equal, 1, nir_type_float, nir_type_float)
|
||||
BINOP_REDUCE(fany_nequal, 1, nir_type_float, nir_type_float)
|
||||
|
||||
/**
|
||||
* These comparisons for integer-less hardware return 1.0 and 0.0 for true
|
||||
* and false respectively
|
||||
*/
|
||||
BINOP(slt, nir_type_float) /* Set on Less Than */
|
||||
BINOP(sge, nir_type_float) /* Set on Greater Than or Equal */
|
||||
BINOP(seq, nir_type_float) /* Set on Equal */
|
||||
BINOP(sne, nir_type_float) /* Set on Not Equal */
|
||||
|
||||
/*@}*/
|
||||
|
||||
BINOP(ishl, nir_type_int)
|
||||
BINOP(ishr, nir_type_int)
|
||||
BINOP(ushr, nir_type_unsigned)
|
||||
|
||||
/**
|
||||
* \name bitwise logic operators
|
||||
*
|
||||
* These are also used as boolean and, or, xor for hardware supporting
|
||||
* integers.
|
||||
*/
|
||||
/*@{*/
|
||||
BINOP(iand, nir_type_unsigned)
|
||||
BINOP(ior, nir_type_unsigned)
|
||||
BINOP(ixor, nir_type_unsigned)
|
||||
/*@{*/
|
||||
|
||||
/**
|
||||
* \name floating point logic operators
|
||||
*
|
||||
* These use (src != 0.0) for testing the truth of the input, and output 1.0
|
||||
* for true and 0.0 for false
|
||||
*/
|
||||
BINOP(fand, nir_type_float)
|
||||
BINOP(for, nir_type_float)
|
||||
BINOP(fxor, nir_type_float)
|
||||
|
||||
BINOP_REDUCE(fdot, 1, nir_type_float, nir_type_float)
|
||||
|
||||
BINOP(fmin, nir_type_float)
|
||||
BINOP(imin, nir_type_int)
|
||||
BINOP(umin, nir_type_unsigned)
|
||||
BINOP(fmax, nir_type_float)
|
||||
BINOP(imax, nir_type_int)
|
||||
BINOP(umax, nir_type_unsigned)
|
||||
|
||||
BINOP(fpow, nir_type_float)
|
||||
|
||||
BINOP_HORIZ(pack_half_2x16_split, 1, nir_type_unsigned, 1, nir_type_float, 1, nir_type_float)
|
||||
|
||||
BINOP(bfm, nir_type_unsigned)
|
||||
|
||||
BINOP(ldexp, nir_type_unsigned)
|
||||
|
||||
/**
|
||||
* Combines the first component of each input to make a 2-component vector.
|
||||
*/
|
||||
BINOP_HORIZ(vec2, 2, nir_type_unsigned, 1, nir_type_unsigned, 1, nir_type_unsigned)
|
||||
|
||||
#define TRIOP(name, type) \
|
||||
OPCODE(name, 3, true, 0, type, ARR(0, 0, 0), ARR(type, type, type))
|
||||
#define TRIOP_HORIZ(name, output_size, src1_size, src2_size, src3_size) \
|
||||
OPCODE(name, 3, false, output_size, nir_type_unsigned, \
|
||||
ARR(src1_size, src2_size, src3_size), \
|
||||
ARR(nir_type_unsigned, nir_type_unsigned, nir_type_unsigned))
|
||||
|
||||
TRIOP(ffma, nir_type_float)
|
||||
|
||||
TRIOP(flrp, nir_type_float)
|
||||
|
||||
/**
|
||||
* \name Conditional Select
|
||||
*
|
||||
* A vector conditional select instruction (like ?:, but operating per-
|
||||
* component on vectors). There are two versions, one for floating point
|
||||
* bools (0.0 vs 1.0) and one for integer bools (0 vs ~0).
|
||||
*/
|
||||
|
||||
OPCODE(fcsel, 3, true, 0, nir_type_float, ARR(1, 0, 0),
|
||||
ARR(nir_type_float, nir_type_float, nir_type_float))
|
||||
OPCODE(bcsel, 3, true, 0, nir_type_unsigned, ARR(1, 0, 0),
|
||||
ARR(nir_type_bool, nir_type_unsigned, nir_type_unsigned))
|
||||
|
||||
TRIOP(bfi, nir_type_unsigned)
|
||||
|
||||
TRIOP(ubitfield_extract, nir_type_unsigned)
|
||||
OPCODE(ibitfield_extract, 3, true, 0, nir_type_int, ARR(0, 0, 0),
|
||||
ARR(nir_type_int, nir_type_unsigned, nir_type_unsigned))
|
||||
|
||||
/**
|
||||
* Combines the first component of each input to make a 3-component vector.
|
||||
*/
|
||||
TRIOP_HORIZ(vec3, 3, 1, 1, 1)
|
||||
|
||||
#define QUADOP(name) \
|
||||
OPCODE(name, 4, true, 0, nir_type_unsigned, ARR(0, 0, 0, 0), \
|
||||
ARR(nir_type_unsigned, nir_type_unsigned, nir_type_unsigned, nir_type_unsigned))
|
||||
#define QUADOP_HORIZ(name, output_size, src1_size, src2_size, src3_size, \
|
||||
src4_size) \
|
||||
OPCODE(name, 4, false, output_size, nir_type_unsigned, \
|
||||
ARR(src1_size, src2_size, src3_size, src4_size), \
|
||||
ARR(nir_type_unsigned, nir_type_unsigned, nir_type_unsigned, nir_type_unsigned))
|
||||
|
||||
QUADOP(bitfield_insert)
|
||||
|
||||
QUADOP_HORIZ(vec4, 4, 1, 1, 1, 1)
|
||||
|
||||
LAST_OPCODE(vec4)
|
||||
Reference in New Issue
Block a user