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intel/fs: Use new F16TO32 helpers for unpack_half_split_* opcodes

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This gets us a MOV at the IR level on Gfx8+ which should be more
optimizable than F16TO32.  It also removes confusion about which
pipe which the instruction will run on.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21783>
This commit is contained in:
Kenneth Graunke
2023-03-07 20:47:02 -08:00
committed by Marge Bot
parent 78bf53904e
commit 309ec3725a
1 changed files with 2 additions and 4 deletions
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6
src/intel/compiler/brw_fs_nir.cpp
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@@ -1653,16 +1653,14 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 & execution_mode);
FALLTHROUGH;
case nir_op_unpack_half_2x16_split_x:
inst = bld.emit(BRW_OPCODE_F16TO32, result,
subscript(op[0], BRW_REGISTER_TYPE_UW, 0));
inst = bld.F16TO32(result, subscript(op[0], BRW_REGISTER_TYPE_HF, 0));
break;
case nir_op_unpack_half_2x16_split_y_flush_to_zero:
assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 & execution_mode);
FALLTHROUGH;
case nir_op_unpack_half_2x16_split_y:
inst = bld.emit(BRW_OPCODE_F16TO32, result,
subscript(op[0], BRW_REGISTER_TYPE_UW, 1));
inst = bld.F16TO32(result, subscript(op[0], BRW_REGISTER_TYPE_HF, 1));
break;
case nir_op_pack_64_2x32_split: