radeonsi/gfx9: update primitive binning code for EQAA
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
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@@ -66,7 +66,7 @@ static struct uvec2 si_find_bin_size(struct si_screen *sscreen,
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static struct uvec2 si_get_color_bin_size(struct si_context *sctx,
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unsigned cb_target_enabled_4bit)
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{
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unsigned nr_samples = sctx->framebuffer.nr_samples;
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unsigned num_fragments = sctx->framebuffer.nr_color_samples;
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unsigned sum = 0;
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/* Compute the sum of all Bpp. */
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@@ -80,9 +80,9 @@ static struct uvec2 si_get_color_bin_size(struct si_context *sctx,
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}
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/* Multiply the sum by some function of the number of samples. */
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if (nr_samples >= 2) {
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if (num_fragments >= 2) {
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if (si_get_ps_iter_samples(sctx) >= 2)
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sum *= nr_samples;
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sum *= num_fragments;
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else
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sum *= 2;
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}
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@@ -205,7 +205,7 @@ static struct uvec2 si_get_depth_bin_size(struct si_context *sctx)
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unsigned stencil_coeff = rtex->surface.has_stencil &&
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dsa->stencil_enabled ? 1 : 0;
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unsigned sum = 4 * (depth_coeff + stencil_coeff) *
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sctx->framebuffer.nr_samples;
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rtex->buffer.b.b.nr_samples;
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static const si_bin_size_subtable table[] = {
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{
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@@ -393,8 +393,13 @@ void si_emit_dpbb_state(struct si_context *sctx)
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/* Enable DFSM if it's preferred. */
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unsigned punchout_mode = V_028060_FORCE_OFF;
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bool disable_start_of_prim = true;
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bool zs_eqaa_dfsm_bug = sctx->chip_class == GFX9 &&
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sctx->framebuffer.state.zsbuf &&
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sctx->framebuffer.nr_samples !=
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MAX2(1, sctx->framebuffer.state.zsbuf->texture->nr_samples);
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if (sscreen->dfsm_allowed &&
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!zs_eqaa_dfsm_bug &&
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cb_target_enabled_4bit &&
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!G_02880C_KILL_ENABLE(db_shader_control) &&
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/* These two also imply that DFSM is disabled when PS writes to memory. */
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