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intel/perf: Add assert to check if allocated enough query fiels

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Xe2 platforms will have way more query fields and allocation of that
will need to be increased but first lets add a function to return the
max_fields and assert if tried to access more query fields then
allocated.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29899>
This commit is contained in:
José Roberto de Souza
2024-05-30 11:28:28 -07:00
committed by Marge Bot
parent 0a51842f7a
commit 2f2a0bc083
1 changed files with 23 additions and 16 deletions
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39
src/intel/perf/intel_perf.c
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@@ -1313,13 +1313,17 @@ intel_perf_compare_query_names(const void *v1, const void *v2)
return strcmp(q1->name, q2->name);
}
#define MAX_QUERY_FIELDS(devinfo) (5 + 16)
static inline struct intel_perf_query_field *
add_query_register(struct intel_perf_query_field_layout *layout,
add_query_register(struct intel_perf_config *perf_cfg,
enum intel_perf_query_field_type type,
uint16_t offset,
uint16_t size,
uint8_t index)
{
struct intel_perf_query_field_layout *layout = &perf_cfg->query_layout;
/* Align MI_RPC to 64bytes (HW requirement) & 64bit registers to 8bytes
* (shows up nicely in the debugger).
*/
@@ -1328,6 +1332,7 @@ add_query_register(struct intel_perf_query_field_layout *layout,
else if (size % 8 == 0)
layout->size = align(layout->size, 8);
assert(layout->n_fields < MAX_QUERY_FIELDS(perf_cfg->devinfo));
layout->fields[layout->n_fields++] = (struct intel_perf_query_field) {
.mmio_offset = offset,
.location = layout->size,
@@ -1352,33 +1357,34 @@ intel_perf_init_query_fields(struct intel_perf_config *perf_cfg,
/* MI_RPC requires a 64byte alignment. */
layout->alignment = 64;
layout->fields = rzalloc_array(perf_cfg, struct intel_perf_query_field, 5 + 16);
layout->fields = rzalloc_array(perf_cfg, struct intel_perf_query_field,
MAX_QUERY_FIELDS(devinfo));
add_query_register(layout, INTEL_PERF_QUERY_FIELD_TYPE_MI_RPC,
add_query_register(perf_cfg, INTEL_PERF_QUERY_FIELD_TYPE_MI_RPC,
0, 256, 0);
if (use_register_snapshots) {
if (devinfo->ver <= 11) {
struct intel_perf_query_field *field =
add_query_register(layout,
add_query_register(perf_cfg,
INTEL_PERF_QUERY_FIELD_TYPE_SRM_PERFCNT,
PERF_CNT_1_DW0, 8, 0);
field->mask = PERF_CNT_VALUE_MASK;
field = add_query_register(layout,
field = add_query_register(perf_cfg,
INTEL_PERF_QUERY_FIELD_TYPE_SRM_PERFCNT,
PERF_CNT_2_DW0, 8, 1);
field->mask = PERF_CNT_VALUE_MASK;
}
if (devinfo->ver == 8 && devinfo->platform != INTEL_PLATFORM_CHV) {
add_query_register(layout,
INTEL_PERF_QUERY_FIELD_TYPE_SRM_RPSTAT,
add_query_register(perf_cfg,
INTEL_PERF_QUERY_FIELD_TYPE_SRM_RPSTAT,
GFX7_RPSTAT1, 4, 0);
}
if (devinfo->ver >= 9) {
add_query_register(layout,
add_query_register(perf_cfg,
INTEL_PERF_QUERY_FIELD_TYPE_SRM_RPSTAT,
GFX9_RPSTAT0, 4, 0);
}
@@ -1386,33 +1392,33 @@ intel_perf_init_query_fields(struct intel_perf_config *perf_cfg,
if (!can_use_mi_rpc_bc_counters(devinfo)) {
if (devinfo->ver >= 8 && devinfo->ver <= 11) {
for (uint32_t i = 0; i < GFX8_N_OA_PERF_B32; i++) {
add_query_register(layout, INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_B,
add_query_register(perf_cfg, INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_B,
GFX8_OA_PERF_B32(i), 4, i);
}
for (uint32_t i = 0; i < GFX8_N_OA_PERF_C32; i++) {
add_query_register(layout, INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_C,
add_query_register(perf_cfg, INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_C,
GFX8_OA_PERF_C32(i), 4, i);
}
} else if (devinfo->verx10 == 120) {
for (uint32_t i = 0; i < GFX12_N_OAG_PERF_B32; i++) {
add_query_register(layout, INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_B,
add_query_register(perf_cfg, INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_B,
GFX12_OAG_PERF_B32(i), 4, i);
}
for (uint32_t i = 0; i < GFX12_N_OAG_PERF_C32; i++) {
add_query_register(layout, INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_C,
add_query_register(perf_cfg, INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_C,
GFX12_OAG_PERF_C32(i), 4, i);
}
} else if (devinfo->verx10 == 125) {
add_query_register(layout, INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_A,
add_query_register(perf_cfg, INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_A,
GFX125_OAG_PERF_A36, 4, 36);
add_query_register(layout, INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_A,
add_query_register(perf_cfg, INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_A,
GFX125_OAG_PERF_A37, 4, 37);
for (uint32_t i = 0; i < GFX12_N_OAG_PERF_B32; i++) {
add_query_register(layout, INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_B,
add_query_register(perf_cfg, INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_B,
GFX12_OAG_PERF_B32(i), 4, i);
}
for (uint32_t i = 0; i < GFX12_N_OAG_PERF_C32; i++) {
add_query_register(layout, INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_C,
add_query_register(perf_cfg, INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_C,
GFX12_OAG_PERF_C32(i), 4, i);
}
}
@@ -1432,6 +1438,7 @@ intel_perf_init_metrics(struct intel_perf_config *perf_cfg,
bool include_pipeline_statistics,
bool use_register_snapshots)
{
perf_cfg->devinfo = devinfo;
intel_perf_init_query_fields(perf_cfg, devinfo, use_register_snapshots);
if (include_pipeline_statistics) {