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i965: Use correct VertStride on align16 instructions.

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In commit c35fa7a, we changed the "width" of DF source registers to 2,
which is conceptually fine. Unfortunately a VertStride of 2 is not
allowed by align16 instructions on IVB/BYT, and the regular VertStride
of 4 works fine in any case.

See generated_tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/vs-round-double.shader_test
for example:

cmp.ge.f0(8)    g18<1>DF        g1<0>.xyxyDF    -g8<2>DF        { align16 1Q };
        ERROR: In Align16 mode, only VertStride of 0 or 4 is allowed
cmp.ge.f0(8)    g19<1>DF        g1<0>.xyxyDF    -g9<2>DF        { align16 2N };
        ERROR: In Align16 mode, only VertStride of 0 or 4 is allowed

v2:
- Add spec quote (Curro).
- Change the condition to only BRW_VERTICAL_STRIDE_2 (Curro)

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
This commit is contained in:
Matt Turner
2017-01-20 13:35:33 -08:00
committed by Francisco Jerez
parent d8441e2276
commit 2eeb1b0ad9
1 changed files with 34 additions and 10 deletions
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44
src/intel/compiler/brw_eu_emit.c
View File

@@ -511,13 +511,25 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
brw_inst_set_src0_da16_swiz_w(devinfo, inst, brw_inst_set_src0_da16_swiz_w(devinfo, inst,
BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_W)); BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_W));
/* This is an oddity of the fact we're using the same if (reg.vstride == BRW_VERTICAL_STRIDE_8) {
* descriptions for registers in align_16 as align_1: /* This is an oddity of the fact we're using the same
*/ * descriptions for registers in align_16 as align_1:
if (reg.vstride == BRW_VERTICAL_STRIDE_8) */
brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4); brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4);
else } else if (devinfo->gen == 7 && !devinfo->is_haswell &&
reg.type == BRW_REGISTER_TYPE_DF &&
reg.vstride == BRW_VERTICAL_STRIDE_2) {
/* From SNB PRM:
*
* "For Align16 access mode, only encodings of 0000 and 0011
* are allowed. Other codes are reserved."
*
* Presumably the DevSNB behavior applies to IVB as well.
*/
brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4);
} else {
brw_inst_set_src0_vstride(devinfo, inst, reg.vstride); brw_inst_set_src0_vstride(devinfo, inst, reg.vstride);
}
} }
} }
} }
@@ -593,13 +605,25 @@ brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
brw_inst_set_src1_da16_swiz_w(devinfo, inst, brw_inst_set_src1_da16_swiz_w(devinfo, inst,
BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_W)); BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_W));
/* This is an oddity of the fact we're using the same if (reg.vstride == BRW_VERTICAL_STRIDE_8) {
* descriptions for registers in align_16 as align_1: /* This is an oddity of the fact we're using the same
*/ * descriptions for registers in align_16 as align_1:
if (reg.vstride == BRW_VERTICAL_STRIDE_8) */
brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4); brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4);
else } else if (devinfo->gen == 7 && !devinfo->is_haswell &&
reg.type == BRW_REGISTER_TYPE_DF &&
reg.vstride == BRW_VERTICAL_STRIDE_2) {
/* From SNB PRM:
*
* "For Align16 access mode, only encodings of 0000 and 0011
* are allowed. Other codes are reserved."
*
* Presumably the DevSNB behavior applies to IVB as well.
*/
brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_4);
} else {
brw_inst_set_src1_vstride(devinfo, inst, reg.vstride); brw_inst_set_src1_vstride(devinfo, inst, reg.vstride);
}
} }
} }
} }