intel,nir: Lower TXD with a bindless sampler

When we have a bindless sampler, we need an instruction header.  Even in
SIMD8, this pushes the instruction over the sampler message size maximum
of 11 registers.  Instead, we have to lower TXD to TXL.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

src/compiler/nir/nir.h

@@ -3282,6 +3282,12 @@ typedef struct nir_lower_tex_options {
     */
    bool lower_txd_offset_clamp;
 
+   /**
+    * If true, lower nir_texop_txd with min_lod to a nir_texop_txl if the
+    * sampler is bindless.
+    */
+   bool lower_txd_clamp_bindless_sampler;
+
    /**
     * If true, lower nir_texop_txd with min_lod to a nir_texop_txl if the
     * sampler index is not statically determinable to be less than 16.

src/compiler/nir/nir_lower_tex.c

@@ -1100,6 +1100,8 @@ nir_lower_tex_block(nir_block *block, nir_builder *b,
            (options->lower_txd_shadow && tex->is_shadow) ||
            (options->lower_txd_shadow_clamp && tex->is_shadow && has_min_lod) ||
            (options->lower_txd_offset_clamp && has_offset && has_min_lod) ||
+           (options->lower_txd_clamp_bindless_sampler && has_min_lod &&
+            nir_tex_instr_src_index(tex, nir_tex_src_sampler_handle) != -1) ||
            (options->lower_txd_clamp_if_sampler_index_not_lt_16 &&
             has_min_lod && !sampler_index_lt(tex, 16)) ||
            (options->lower_txd_cube_map &&

src/intel/compiler/brw_nir.c

@@ -949,6 +949,7 @@ brw_nir_apply_sampler_key(nir_shader *nir,
 {
    const struct gen_device_info *devinfo = compiler->devinfo;
    nir_lower_tex_options tex_options = {
+      .lower_txd_clamp_bindless_sampler = true,
       .lower_txd_clamp_if_sampler_index_not_lt_16 = true,
    };