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drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.

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This commit is contained in:
Eric Anholt
2008-07-11 14:16:36 -07:00
parent def6e4f420
commit 2e841880cf
18 changed files with 250 additions and 298 deletions
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2
src/mesa/drivers/dri/i965/brw_misc_state.c
View File

@@ -232,7 +232,7 @@ static void emit_depthbuffer(struct brw_context *brw)
OUT_BATCH(((region->pitch * region->cpp) - 1) |
(format << 18) |
(BRW_TILEWALK_YMAJOR << 26) |
(region->tiled << 27) |
((region->tiling != I915_TILING_NONE) << 27) |
(BRW_SURFACE_2D << 29));
OUT_RELOC(region->buffer,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,

37
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
View File

@@ -154,9 +154,28 @@ struct brw_wm_surface_key {
GLint first_level, last_level;
GLint width, height, depth;
GLint pitch, cpp;
GLboolean tiled;
uint32_t tiling;
};
static void
brw_set_surface_tiling(struct brw_surface_state *surf, uint32_t tiling)
{
switch (tiling) {
case I915_TILING_NONE:
surf->ss3.tiled_surface = 0;
surf->ss3.tile_walk = 0;
break;
case I915_TILING_X:
surf->ss3.tiled_surface = 1;
surf->ss3.tile_walk = BRW_TILEWALK_XMAJOR;
break;
case I915_TILING_Y:
surf->ss3.tiled_surface = 1;
surf->ss3.tile_walk = BRW_TILEWALK_YMAJOR;
break;
}
}
static dri_bo *
brw_create_texture_surface( struct brw_context *brw,
struct brw_wm_surface_key *key )
@@ -179,9 +198,7 @@ brw_create_texture_surface( struct brw_context *brw,
surf.ss2.mip_count = key->last_level - key->first_level;
surf.ss2.width = key->width - 1;
surf.ss2.height = key->height - 1;
surf.ss3.tile_walk = BRW_TILEWALK_XMAJOR;
surf.ss3.tiled_surface = key->tiled;
brw_set_surface_tiling(&surf, key->tiling);
surf.ss3.pitch = (key->pitch * key->cpp) - 1;
surf.ss3.depth = key->depth - 1;
@@ -234,7 +251,7 @@ brw_update_texture_surface( GLcontext *ctx, GLuint unit )
key.pitch = intelObj->mt->pitch;
key.cpp = intelObj->mt->cpp;
key.depth = firstImage->Depth;
key.tiled = intelObj->mt->region->tiled;
key.tiling = intelObj->mt->region->tiling;
ret |= dri_bufmgr_check_aperture_space(key.bo);
@@ -267,7 +284,8 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
unsigned int surface_format;
unsigned int width, height, cpp;
GLubyte color_mask[4];
GLboolean tiled, color_blend;
GLboolean color_blend;
uint32_t tiling;
} key;
memset(&key, 0, sizeof(key));
@@ -280,7 +298,7 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
else
key.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
key.tiled = region->tiled;
key.tiling = region->tiling;
key.width = region->pitch; /* XXX: not really! */
key.height = region->height;
key.cpp = region->cpp;
@@ -289,7 +307,7 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
} else {
key.surface_type = BRW_SURFACE_NULL;
key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
key.tiled = 0;
key.tiling = 0;
key.width = 1;
key.height = 1;
key.cpp = 4;
@@ -319,8 +337,7 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
surf.ss2.width = key.width - 1;
surf.ss2.height = key.height - 1;
surf.ss3.tile_walk = BRW_TILEWALK_XMAJOR;
surf.ss3.tiled_surface = key.tiled;
brw_set_surface_tiling(&surf, key.tiling);
surf.ss3.pitch = (key.width * key.cpp) - 1;
/* _NEW_COLOR */

24
src/mesa/drivers/dri/intel/intel_blit.c
View File

@@ -106,11 +106,11 @@ intelCopyBuffer(const __DRIdrawablePrivate * dPriv,
}
#ifndef I915
if (src->tiled) {
if (src->tiling != I915_TILING_NONE) {
CMD |= XY_SRC_TILED;
src_pitch /= 4;
}
if (dst->tiled) {
if (dst->tiling != I915_TILING_NONE) {
CMD |= XY_DST_TILED;
dst_pitch /= 4;
}
@@ -178,7 +178,7 @@ intelEmitFillBlit(struct intel_context *intel,
GLshort dst_pitch,
dri_bo *dst_buffer,
GLuint dst_offset,
GLboolean dst_tiled,
uint32_t dst_tiling,
GLshort x, GLshort y,
GLshort w, GLshort h,
GLuint color)
@@ -203,7 +203,7 @@ intelEmitFillBlit(struct intel_context *intel,
return;
}
#ifndef I915
if (dst_tiled) {
if (dst_tiling != I915_TILING_NONE) {
CMD |= XY_DST_TILED;
dst_pitch /= 4;
}
@@ -259,11 +259,11 @@ intelEmitCopyBlit(struct intel_context *intel,
GLshort src_pitch,
dri_bo *src_buffer,
GLuint src_offset,
GLboolean src_tiled,
uint32_t src_tiling,
GLshort dst_pitch,
dri_bo *dst_buffer,
GLuint dst_offset,
GLboolean dst_tiled,
uint32_t dst_tiling,
GLshort src_x, GLshort src_y,
GLshort dst_x, GLshort dst_y,
GLshort w, GLshort h,
@@ -309,11 +309,11 @@ intelEmitCopyBlit(struct intel_context *intel,
}
#ifndef I915
if (dst_tiled) {
if (dst_tiling != I915_TILING_NONE) {
CMD |= XY_DST_TILED;
dst_pitch /= 4;
}
if (src_tiled) {
if (src_tiling != I915_TILING_NONE) {
CMD |= XY_SRC_TILED;
src_pitch /= 4;
}
@@ -512,7 +512,7 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask)
}
#ifndef I915
if (irb_region->tiled) {
if (irb_region->tiling != I915_TILING_NONE) {
CMD |= XY_DST_TILED;
pitch /= 4;
}
@@ -563,7 +563,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
GLshort dst_pitch,
dri_bo *dst_buffer,
GLuint dst_offset,
GLboolean dst_tiled,
uint32_t dst_tiling,
GLshort x, GLshort y,
GLshort w, GLshort h,
GLenum logic_op)
@@ -593,7 +593,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
if (cpp == 4)
opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
#ifndef I915
if (dst_tiled) {
if (dst_tiling != I915_TILING_NONE) {
opcode |= XY_DST_TILED;
dst_pitch /= 4;
}
@@ -606,7 +606,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
br13 |= BR13_8888;
blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
if (dst_tiled)
if (dst_tiling != I915_TILING_NONE)
blit_cmd |= XY_DST_TILED;
BEGIN_BATCH(8 + 3, REFERENCES_CLIPRECTS);

8
src/mesa/drivers/dri/intel/intel_blit.h
View File

@@ -42,11 +42,11 @@ extern void intelEmitCopyBlit(struct intel_context *intel,
GLshort src_pitch,
dri_bo *src_buffer,
GLuint src_offset,
GLboolean src_tiled,
uint32_t src_tiling,
GLshort dst_pitch,
dri_bo *dst_buffer,
GLuint dst_offset,
GLboolean dst_tiled,
uint32_t dst_tiling,
GLshort srcx, GLshort srcy,
GLshort dstx, GLshort dsty,
GLshort w, GLshort h,
@@ -57,7 +57,7 @@ extern void intelEmitFillBlit(struct intel_context *intel,
GLshort dst_pitch,
dri_bo *dst_buffer,
GLuint dst_offset,
GLboolean dst_tiled,
uint32_t dst_tiling,
GLshort x, GLshort y,
GLshort w, GLshort h, GLuint color);
@@ -69,7 +69,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
GLshort dst_pitch,
dri_bo *dst_buffer,
GLuint dst_offset,
GLboolean dst_tiled,
uint32_t dst_tiling,
GLshort x, GLshort y,
GLshort w, GLshort h,
GLenum logic_op);

3
src/mesa/drivers/dri/intel/intel_context.c
View File

@@ -703,9 +703,6 @@ intelInitContext(struct intel_context *intel,
intel->no_rast = 1;
}
intel->tiling_swizzle_mode = driQueryOptioni(&intel->optionCache,
"swizzle_mode");
/* Disable all hardware rendering (skip emitting batches and fences/waits
* to the kernel)
*/

1
src/mesa/drivers/dri/intel/intel_context.h
View File

@@ -266,7 +266,6 @@ struct intel_context
GLuint lastStamp;
GLboolean no_hw;
int tiling_swizzle_mode;
/**
* Configuration cache

21
src/mesa/drivers/dri/intel/intel_fbo.c
View File

@@ -294,10 +294,6 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
rb->Width = width;
rb->Height = height;
/* This sets the Get/PutRow/Value functions */
/* XXX can we choose a different tile here? */
intel_set_span_functions(&irb->Base, INTEL_TILE_NONE);
return GL_TRUE;
}
}
@@ -376,8 +372,7 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *rb,
* not a user-created renderbuffer.
*/
struct intel_renderbuffer *
intel_create_renderbuffer(intelScreenPrivate *intelScreen,
GLenum intFormat, enum tiling_mode tiling)
intel_create_renderbuffer(GLenum intFormat)
{
GET_CURRENT_CONTEXT(ctx);
@@ -444,20 +439,10 @@ intel_create_renderbuffer(intelScreenPrivate *intelScreen,
irb->Base.InternalFormat = intFormat;
irb->tiling = tiling;
/* intel-specific methods */
irb->Base.Delete = intel_delete_renderbuffer;
irb->Base.AllocStorage = intel_alloc_window_storage;
irb->Base.GetPointer = intel_get_pointer;
/* This sets the Get/PutRow/Value functions. In classic mode, all access
* is through the aperture and will be swizzled by the fence registers, so
* we don't need the span functions to perfom tile swizzling
*/
if (intelScreen->ttm)
intel_set_span_functions(&irb->Base, tiling);
else
intel_set_span_functions(&irb->Base, INTEL_TILE_NONE);
return irb;
}
@@ -568,7 +553,6 @@ intel_update_wrapper(GLcontext *ctx, struct intel_renderbuffer *irb,
irb->Base.Delete = intel_delete_renderbuffer;
irb->Base.AllocStorage = intel_nop_alloc_storage;
intel_set_span_functions(&irb->Base, irb->tiling);
irb->RenderToTexture = GL_TRUE;
@@ -596,9 +580,6 @@ intel_wrap_texture(GLcontext * ctx, struct gl_texture_image *texImage)
_mesa_init_renderbuffer(&irb->Base, name);
irb->Base.ClassID = INTEL_RB_CLASS;
/* XXX can we fix this? */
irb->tiling = INTEL_TILE_NONE;
if (!intel_update_wrapper(ctx, irb, texImage)) {
_mesa_free(irb);
return NULL;

4
src/mesa/drivers/dri/intel/intel_fbo.h
View File

@@ -72,7 +72,6 @@ struct intel_renderbuffer
struct intel_region *region;
void *pfMap; /* possibly paged flipped map pointer */
GLuint pfPitch; /* possibly paged flipped pitch */
enum tiling_mode tiling;
GLboolean RenderToTexture; /* RTT? */
GLuint PairedDepth; /**< only used if this is a depth renderbuffer */
@@ -91,8 +90,7 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *irb,
struct intel_region *region);
extern struct intel_renderbuffer *
intel_create_renderbuffer(intelScreenPrivate *intelScreen,
GLenum intFormat, enum tiling_mode tiling);
intel_create_renderbuffer(GLenum intFormat);
extern void intel_fbo_init(struct intel_context *intel);

2
src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
View File

@@ -293,7 +293,7 @@ do_blit_bitmap( GLcontext *ctx,
dst->pitch,
dst->buffer,
0,
dst->tiled,
dst->tiling,
rect.x1 + px,
rect.y2 - (py + h),
w, h,

4
src/mesa/drivers/dri/intel/intel_pixel_copy.c
View File

@@ -337,8 +337,8 @@ do_blit_copypixels(GLcontext * ctx,
continue;
intelEmitCopyBlit(intel, dst->cpp,
src->pitch, src->buffer, 0, src->tiled,
dst->pitch, dst->buffer, 0, dst->tiled,
src->pitch, src->buffer, 0, src->tiling,
dst->pitch, dst->buffer, 0, dst->tiling,
clip_x + delta_x, clip_y + delta_y, /* srcx, srcy */
clip_x, clip_y, /* dstx, dsty */
clip_w, clip_h,

2
src/mesa/drivers/dri/intel/intel_pixel_draw.c
View File

@@ -314,7 +314,7 @@ do_blit_drawpixels(GLcontext * ctx,
intelEmitCopyBlit(intel,
dest->cpp,
rowLength, src_buffer, src_offset, GL_FALSE,
dest->pitch, dest->buffer, 0, dest->tiled,
dest->pitch, dest->buffer, 0, dest->tiling,
rect.x1 - dest_rect.x1,
rect.y2 - dest_rect.y2,
rect.x1,

129
src/mesa/drivers/dri/intel/intel_regions.c
View File

@@ -39,6 +39,9 @@
* last moment.
*/
#include <sys/ioctl.h>
#include <errno.h>
#include "intel_context.h"
#include "intel_regions.h"
#include "intel_blit.h"
@@ -46,6 +49,7 @@
#include "dri_bufmgr.h"
#include "intel_bufmgr.h"
#include "intel_batchbuffer.h"
#include "intel_chipset.h"
#define FILE_DEBUG_FLAG DEBUG_REGION
@@ -76,10 +80,34 @@ intel_region_unmap(struct intel_context *intel, struct intel_region *region)
}
}
static int
intel_set_region_tiling_gem(struct intel_context *intel,
struct intel_region *region,
uint32_t bo_handle)
{
struct drm_i915_gem_get_tiling get_tiling;
int ret;
memset(&get_tiling, 0, sizeof(get_tiling));
get_tiling.handle = bo_handle;
ret = ioctl(intel->driFd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
if (ret != 0) {
fprintf(stderr, "Failed to get tiling state for region: %s\n",
strerror(errno));
return ret;
}
region->tiling = get_tiling.tiling_mode;
region->bit_6_swizzle = get_tiling.swizzle_mode;
return 0;
}
static struct intel_region *
intel_region_alloc_internal(struct intel_context *intel,
GLuint cpp, GLuint pitch, GLuint height,
GLuint tiled, dri_bo *buffer)
dri_bo *buffer)
{
struct intel_region *region;
@@ -93,9 +121,12 @@ intel_region_alloc_internal(struct intel_context *intel,
region->pitch = pitch;
region->height = height; /* needed? */
region->refcount = 1;
region->tiled = tiled;
region->buffer = buffer;
/* Default to no tiling */
region->tiling = I915_TILING_NONE;
region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE;
return region;
}
@@ -108,20 +139,26 @@ intel_region_alloc(struct intel_context *intel,
buffer = dri_bo_alloc(intel->bufmgr, "region",
pitch * cpp * height, 64);
return intel_region_alloc_internal(intel, cpp, pitch, height, 0, buffer);
return intel_region_alloc_internal(intel, cpp, pitch, height, buffer);
}
struct intel_region *
intel_region_alloc_for_handle(struct intel_context *intel,
GLuint cpp, GLuint pitch, GLuint height,
GLuint tiled, GLuint handle)
GLuint handle)
{
struct intel_region *region;
dri_bo *buffer;
buffer = intel_bo_gem_create_from_name(intel->bufmgr, "region", handle);
buffer = intel_bo_gem_create_from_name(intel->bufmgr, "dri2 region", handle);
return intel_region_alloc_internal(intel,
cpp, pitch, height, tiled, buffer);
region = intel_region_alloc_internal(intel, cpp, pitch, height, buffer);
if (region == NULL)
return region;
intel_set_region_tiling_gem(intel, region, handle);
return region;
}
void
@@ -135,26 +172,34 @@ intel_region_reference(struct intel_region **dst, struct intel_region *src)
}
void
intel_region_release(struct intel_region **region)
intel_region_release(struct intel_region **region_handle)
{
if (!*region)
struct intel_region *region = *region_handle;
if (region == NULL)
return;
DBG("%s %d\n", __FUNCTION__, (*region)->refcount - 1);
DBG("%s %d\n", __FUNCTION__, region->refcount - 1);
ASSERT((*region)->refcount > 0);
(*region)->refcount--;
ASSERT(region->refcount > 0);
region->refcount--;
if ((*region)->refcount == 0) {
assert((*region)->map_refcount == 0);
if (region->refcount == 0) {
assert(region->map_refcount == 0);
if ((*region)->pbo)
(*region)->pbo->region = NULL;
(*region)->pbo = NULL;
dri_bo_unreference((*region)->buffer);
free(*region);
if (region->pbo)
region->pbo->region = NULL;
region->pbo = NULL;
dri_bo_unreference(region->buffer);
if (region->classic_map != NULL) {
drmUnmap(region->classic_map,
region->pitch * region->cpp * region->height);
}
*region = NULL;
free(region);
}
*region_handle = NULL;
}
/*
@@ -269,8 +314,8 @@ intel_region_copy(struct intel_context *intel,
intelEmitCopyBlit(intel,
dst->cpp,
src->pitch, src->buffer, src_offset, src->tiled,
dst->pitch, dst->buffer, dst_offset, dst->tiled,
src->pitch, src->buffer, src_offset, src->tiling,
dst->pitch, dst->buffer, dst_offset, dst->tiling,
srcx, srcy, dstx, dsty, width, height,
GL_COPY);
}
@@ -300,7 +345,7 @@ intel_region_fill(struct intel_context *intel,
intelEmitFillBlit(intel,
dst->cpp,
dst->pitch, dst->buffer, dst_offset, dst->tiled,
dst->pitch, dst->buffer, dst_offset, dst->tiling,
dstx, dsty, width, height, color);
}
@@ -382,8 +427,8 @@ intel_region_cow(struct intel_context *intel, struct intel_region *region)
intelEmitCopyBlit(intel,
region->cpp,
region->pitch, region->buffer, 0, region->tiled,
region->pitch, pbo->buffer, 0, region->tiled,
region->pitch, region->buffer, 0, region->tiling,
region->pitch, pbo->buffer, 0, region->tiling,
0, 0, 0, 0,
region->pitch, region->height,
GL_COPY);
@@ -414,6 +459,7 @@ intel_recreate_static(struct intel_context *intel,
GLuint mem_type)
{
intelScreenPrivate *intelScreen = intel->intelScreen;
int ret;
if (region == NULL) {
region = calloc(sizeof(*region), 1);
@@ -426,20 +472,45 @@ intel_recreate_static(struct intel_context *intel,
region->cpp = intel->ctx.Visual.rgbBits / 8;
region->pitch = intelScreen->pitch;
region->height = intelScreen->height; /* needed? */
region->tiled = region_desc->tiled;
if (intel->ttm) {
assert(region_desc->bo_handle != -1);
region->buffer = intel_bo_gem_create_from_name(intel->bufmgr,
name,
region_desc->bo_handle);
intel_set_region_tiling_gem(intel, region, region_desc->bo_handle);
} else {
ret = drmMap(intel->driFd, region_desc->handle,
region->pitch * region->cpp * region->height,
&region->classic_map);
if (ret != 0) {
fprintf(stderr, "Failed to drmMap %s buffer\n", name);
free(region);
return NULL;
}
region->buffer = intel_bo_fake_alloc_static(intel->bufmgr,
name,
region_desc->offset,
intelScreen->pitch *
intelScreen->height,
region_desc->map);
region->pitch * region->cpp *
region->height,
region->classic_map);
/* The sarea just gives us a boolean for whether it's tiled or not,
* instead of which tiling mode it is. Guess.
*/
if (region_desc->tiled) {
if (IS_965(intel->intelScreen->deviceID) &&
region_desc == &intelScreen->depth)
region->tiling = I915_TILING_Y;
else
region->tiling = I915_TILING_X;
} else {
region->tiling = I915_TILING_NONE;
}
region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE;
}
assert(region->buffer != NULL);

13
src/mesa/drivers/dri/intel/intel_regions.h
View File

@@ -28,6 +28,12 @@
#ifndef INTEL_REGIONS_H
#define INTEL_REGIONS_H
/** @file intel_regions.h
*
* Structure definitions and prototypes for intel_region handling, which is
* the basic structure for rectangular collections of pixels stored in a dri_bo.
*/
#include "mtypes.h"
#include "dri_bufmgr.h"
@@ -53,8 +59,9 @@ struct intel_region
GLuint map_refcount; /**< Reference count for mapping */
GLuint draw_offset; /**< Offset of drawing address within the region */
GLboolean tiled; /**< True if the region is X or Y-tiled. Used on 965. */
uint32_t tiling; /**< Which tiling mode the region is in */
uint32_t bit_6_swizzle; /**< GEM flag for address swizzling requirement */
drmAddress classic_map; /**< drmMap of the region when not in GEM mode */
struct intel_buffer_object *pbo; /* zero-copy uploads */
};
@@ -69,7 +76,7 @@ struct intel_region *intel_region_alloc(struct intel_context *intel,
struct intel_region *
intel_region_alloc_for_handle(struct intel_context *intel,
GLuint cpp, GLuint pitch, GLuint height,
GLuint tiled, unsigned int handle);
unsigned int handle);
void intel_region_reference(struct intel_region **dst,
struct intel_region *src);

129
src/mesa/drivers/dri/intel/intel_screen.c
View File

@@ -69,20 +69,13 @@ PUBLIC const char __driConfigOptions[] =
DRI_CONF_SECTION_QUALITY
DRI_CONF_FORCE_S3TC_ENABLE(false)
DRI_CONF_ALLOW_LARGE_TEXTURES(2)
DRI_CONF_OPT_BEGIN_V(swizzle_mode, enum, 0, "0:2")
DRI_CONF_DESC_BEGIN(en, "Tiling swizzle mode for software fallbacks")
DRI_CONF_ENUM(0, "No swizzling")
DRI_CONF_ENUM(1, "addr[6] = addr[6] ^ addr[9]")
DRI_CONF_ENUM(2, "addr[6] = addr[6] ^ addr[9] ^ addr[10]")
DRI_CONF_DESC_END
DRI_CONF_OPT_END
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
DRI_CONF_NO_RAST(false)
DRI_CONF_SECTION_END
DRI_CONF_END;
const GLuint __driNConfigOptions = 7;
const GLuint __driNConfigOptions = 6;
#ifdef USE_NEW_INTERFACE
static PFNGLXCREATECONTEXTMODES create_context_modes = NULL;
@@ -97,51 +90,6 @@ intelMapScreenRegions(__DRIscreenPrivate * sPriv)
{
intelScreenPrivate *intelScreen = (intelScreenPrivate *) sPriv->private;
if (intelScreen->front.handle) {
if (drmMap(sPriv->fd,
intelScreen->front.handle,
intelScreen->front.size,
(drmAddress *) & intelScreen->front.map) != 0) {
_mesa_problem(NULL, "drmMap(frontbuffer) failed!");
return GL_FALSE;
}
}
else {
_mesa_warning(NULL, "no front buffer handle in intelMapScreenRegions!");
}
if (0)
_mesa_printf("Back 0x%08x ", intelScreen->back.handle);
if (drmMap(sPriv->fd,
intelScreen->back.handle,
intelScreen->back.size,
(drmAddress *) & intelScreen->back.map) != 0) {
intelUnmapScreenRegions(intelScreen);
return GL_FALSE;
}
if (intelScreen->third.handle) {
if (0)
_mesa_printf("Third 0x%08x ", intelScreen->third.handle);
if (drmMap(sPriv->fd,
intelScreen->third.handle,
intelScreen->third.size,
(drmAddress *) & intelScreen->third.map) != 0) {
intelUnmapScreenRegions(intelScreen);
return GL_FALSE;
}
}
if (0)
_mesa_printf("Depth 0x%08x ", intelScreen->depth.handle);
if (drmMap(sPriv->fd,
intelScreen->depth.handle,
intelScreen->depth.size,
(drmAddress *) & intelScreen->depth.map) != 0) {
intelUnmapScreenRegions(intelScreen);
return GL_FALSE;
}
if (0)
_mesa_printf("TEX 0x%08x ", intelScreen->tex.handle);
if (intelScreen->tex.size != 0) {
@@ -154,50 +102,15 @@ intelMapScreenRegions(__DRIscreenPrivate * sPriv)
}
}
if (0)
printf("Mappings: front: %p back: %p third: %p depth: %p tex: %p\n",
intelScreen->front.map,
intelScreen->back.map, intelScreen->third.map,
intelScreen->depth.map, intelScreen->tex.map);
return GL_TRUE;
}
void
intelUnmapScreenRegions(intelScreenPrivate * intelScreen)
{
#define REALLY_UNMAP 1
if (intelScreen->front.map) {
#if REALLY_UNMAP
if (drmUnmap(intelScreen->front.map, intelScreen->front.size) != 0)
printf("drmUnmap front failed!\n");
#endif
intelScreen->front.map = NULL;
}
if (intelScreen->back.map) {
#if REALLY_UNMAP
if (drmUnmap(intelScreen->back.map, intelScreen->back.size) != 0)
printf("drmUnmap back failed!\n");
#endif
intelScreen->back.map = NULL;
}
if (intelScreen->third.map) {
#if REALLY_UNMAP
if (drmUnmap(intelScreen->third.map, intelScreen->third.size) != 0)
printf("drmUnmap third failed!\n");
#endif
intelScreen->third.map = NULL;
}
if (intelScreen->depth.map) {
#if REALLY_UNMAP
drmUnmap(intelScreen->depth.map, intelScreen->depth.size);
intelScreen->depth.map = NULL;
#endif
}
if (intelScreen->tex.map) {
#if REALLY_UNMAP
drmUnmap(intelScreen->tex.map, intelScreen->tex.size);
intelScreen->tex.map = NULL;
#endif
}
}
@@ -341,8 +254,6 @@ intelHandleDrawableConfig(__DRIdrawablePrivate *dPriv,
* attached. */
}
#define BUFFER_FLAG_TILED 0x0100
/**
* DRI2 entrypoint
*/
@@ -355,7 +266,6 @@ intelHandleBufferAttach(__DRIdrawablePrivate *dPriv,
struct intel_renderbuffer *rb;
struct intel_region *region;
struct intel_context *intel = pcp->driverPrivate;
GLuint tiled;
switch (ba->buffer.attachment) {
case DRI_DRAWABLE_BUFFER_FRONT_LEFT:
@@ -389,10 +299,9 @@ intelHandleBufferAttach(__DRIdrawablePrivate *dPriv,
return;
#endif
tiled = (ba->buffer.flags & BUFFER_FLAG_TILED) > 0;
region = intel_region_alloc_for_handle(intel, ba->buffer.cpp,
ba->buffer.pitch / ba->buffer.cpp,
dPriv->h, tiled,
dPriv->h,
ba->buffer.handle);
intel_renderbuffer_set_region(rb, region);
@@ -528,7 +437,6 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
GLboolean swStencil = (mesaVis->stencilBits > 0 &&
mesaVis->depthBits != 24);
GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8);
enum tiling_mode tiling;
struct intel_framebuffer *intel_fb = CALLOC_STRUCT(intel_framebuffer);
@@ -538,46 +446,29 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
_mesa_initialize_framebuffer(&intel_fb->Base, mesaVis);
/* setup the hardware-based renderbuffers */
/* We get only a boolean value from the DDX for whether tiling is
* enabled, so we have to guess when it's Y and not X (965 depth).
*/
{
tiling = screen->front.tiled ? INTEL_TILE_X : INTEL_TILE_NONE;
intel_fb->color_rb[0] = intel_create_renderbuffer(screen,
rgbFormat, tiling);
intel_fb->color_rb[0] = intel_create_renderbuffer(rgbFormat);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_FRONT_LEFT,
&intel_fb->color_rb[0]->Base);
}
if (mesaVis->doubleBufferMode) {
tiling = screen->back.tiled ? INTEL_TILE_X : INTEL_TILE_NONE;
intel_fb->color_rb[1] = intel_create_renderbuffer(screen,
rgbFormat, tiling);
intel_fb->color_rb[1] = intel_create_renderbuffer(rgbFormat);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_BACK_LEFT,
&intel_fb->color_rb[1]->Base);
if (screen->third.handle) {
struct gl_renderbuffer *tmp_rb = NULL;
tiling = screen->third.tiled ? INTEL_TILE_X : INTEL_TILE_NONE;
intel_fb->color_rb[2] = intel_create_renderbuffer(screen,
rgbFormat,
tiling);
intel_fb->color_rb[2] = intel_create_renderbuffer(rgbFormat);
_mesa_reference_renderbuffer(&tmp_rb, &intel_fb->color_rb[2]->Base);
}
}
#ifdef I915
tiling = screen->depth.tiled ? INTEL_TILE_X : INTEL_TILE_NONE;
#else
tiling = screen->depth.tiled ? INTEL_TILE_Y : INTEL_TILE_NONE;
#endif
if (mesaVis->depthBits == 24) {
if (mesaVis->stencilBits == 8) {
/* combined depth/stencil buffer */
struct intel_renderbuffer *depthStencilRb
= intel_create_renderbuffer(screen,
GL_DEPTH24_STENCIL8_EXT, tiling);
= intel_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT);
/* note: bind RB to two attachment points */
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH,
&depthStencilRb->Base);
@@ -585,8 +476,7 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
&depthStencilRb->Base);
} else {
struct intel_renderbuffer *depthRb
= intel_create_renderbuffer(screen,
GL_DEPTH_COMPONENT24, tiling);
= intel_create_renderbuffer(GL_DEPTH_COMPONENT24);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH,
&depthRb->Base);
}
@@ -594,8 +484,7 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
else if (mesaVis->depthBits == 16) {
/* just 16-bit depth buffer, no hw stencil */
struct intel_renderbuffer *depthRb
= intel_create_renderbuffer(screen,
GL_DEPTH_COMPONENT16, tiling);
= intel_create_renderbuffer(GL_DEPTH_COMPONENT16);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH, &depthRb->Base);
}

6
src/mesa/drivers/dri/intel/intel_screen.h
View File

@@ -33,12 +33,6 @@
#include "i915_drm.h"
#include "xmlconfig.h"
enum tiling_mode {
INTEL_TILE_NONE,
INTEL_TILE_X,
INTEL_TILE_Y
};
/* XXX: change name or eliminate to avoid conflict with "struct
* intel_region"!!!
*/

142
src/mesa/drivers/dri/intel/intel_span.c
View File

@@ -39,6 +39,10 @@
#include "swrast/swrast.h"
static void
intel_set_span_functions(struct intel_context *intel,
struct gl_renderbuffer *rb);
/*
* Deal with tiled surfaces
*/
@@ -111,39 +115,26 @@ static GLubyte *x_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
tile_off = (y_tile_off << 9) + x_tile_off;
/* bit swizzling tricks your parents never told you about:
*
* The specs say that the X tiling layout is just 8 512-byte rows
* packed into a page. It turns out that there's some additional
* swizzling of bit 6 to reduce cache aliasing issues. Experimental
* results below:
*
* line bit GM965 945G/Q965
* 9 10 11
* 0 0 0 0 0 0
* 1 0 1 0 1 1
* 2 1 0 0 1 1
* 3 1 1 0 0 0
* 4 0 0 1 1 0
* 5 0 1 1 0 1
* 6 1 0 1 0 1
* 7 1 1 1 1 0
*
* So we see that the GM965 is bit 6 ^ 9 ^ 10 ^ 11, while other
* parts were just 6 ^ 9 ^ 10. However, some systems, including a
* GM965 we've seen, don't perform the swizzling at all. Information
* on how to detect it through register reads is expected soon.
*/
switch (intel->tiling_swizzle_mode) {
case 0:
switch (irb->region->bit_6_swizzle) {
case I915_BIT_6_SWIZZLE_NONE:
break;
case 1:
case I915_BIT_6_SWIZZLE_9:
tile_off ^= ((tile_off >> 3) & 64);
break;
case I915_BIT_6_SWIZZLE_9_10:
tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
break;
case 2:
case I915_BIT_6_SWIZZLE_9_11:
tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
break;
case I915_BIT_6_SWIZZLE_9_10_11:
tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
((tile_off >> 5) & 64);
break;
default:
fprintf(stderr, "Unknown tile swizzling mode %d\n",
irb->region->bit_6_swizzle);
exit(1);
}
tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
@@ -184,15 +175,28 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) +
(x_tile_off & 0xf);
switch (intel->tiling_swizzle_mode) {
case 0:
switch (irb->region->bit_6_swizzle) {
case I915_BIT_6_SWIZZLE_NONE:
break;
case 1:
tile_off ^= (tile_off >> 3) & 64;
case I915_BIT_6_SWIZZLE_9:
tile_off ^= ((tile_off >> 3) & 64);
break;
case 2:
case I915_BIT_6_SWIZZLE_9_10:
tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
break;
case I915_BIT_6_SWIZZLE_9_11:
tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
break;
case I915_BIT_6_SWIZZLE_9_10_11:
tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
((tile_off >> 5) & 64);
break;
default:
fprintf(stderr, "Unknown tile swizzling mode %d\n",
irb->region->bit_6_swizzle);
exit(1);
}
tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
return buf + tile_base + tile_off;
@@ -491,9 +495,8 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
for (j = 0; j < ctx->DrawBuffer->_NumColorDrawBuffers; j++) {
struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[j];
irb = intel_renderbuffer(rb);
if (irb) {
/* this is a user-created intel_renderbuffer */
if (irb->region) {
if (irb && irb->region) {
intel_set_span_functions(intel, rb);
if (map)
intel_region_map(intel, irb->region);
else
@@ -502,7 +505,6 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
irb->pfPitch = irb->region->pitch;
}
}
}
/* check for render to textures */
for (i = 0; i < BUFFER_COUNT; i++) {
@@ -526,6 +528,7 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
/* color read buffers */
irb = intel_renderbuffer(ctx->ReadBuffer->_ColorReadBuffer);
if (irb && irb->region) {
intel_set_span_functions(intel, ctx->ReadBuffer->_ColorReadBuffer);
if (map)
intel_region_map(intel, irb->region);
else
@@ -568,6 +571,8 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
irb = intel_renderbuffer(ctx->DrawBuffer->_DepthBuffer->Wrapped);
if (irb && irb->region) {
if (map) {
intel_set_span_functions(intel,
ctx->DrawBuffer->_DepthBuffer->Wrapped);
intel_region_map(intel, irb->region);
irb->pfMap = irb->region->map;
irb->pfPitch = irb->region->pitch;
@@ -585,6 +590,8 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
irb = intel_renderbuffer(ctx->DrawBuffer->_StencilBuffer->Wrapped);
if (irb && irb->region) {
if (map) {
intel_set_span_functions(intel,
ctx->DrawBuffer->_StencilBuffer->Wrapped);
intel_region_map(intel, irb->region);
irb->pfMap = irb->region->map;
irb->pfPitch = irb->region->pitch;
@@ -615,15 +622,6 @@ intelSpanRenderStart(GLcontext * ctx)
intelFlush(&intel->ctx);
LOCK_HARDWARE(intel);
#if 0
/* Just map the framebuffer and all textures. Bufmgr code will
* take care of waiting on the necessary fences:
*/
intel_region_map(intel, intel->front_region);
intel_region_map(intel, intel->back_region);
intel_region_map(intel, intel->depth_region);
#endif
for (i = 0; i < ctx->Const.MaxTextureCoordUnits; i++) {
if (ctx->Texture.Unit[i]._ReallyEnabled) {
struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
@@ -646,14 +644,6 @@ intelSpanRenderFinish(GLcontext * ctx)
_swrast_flush(ctx);
/* Now unmap the framebuffer:
*/
#if 0
intel_region_unmap(intel, intel->front_region);
intel_region_unmap(intel, intel->back_region);
intel_region_unmap(intel, intel->depth_region);
#endif
for (i = 0; i < ctx->Const.MaxTextureCoordUnits; i++) {
if (ctx->Texture.Unit[i]._ReallyEnabled) {
struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
@@ -680,20 +670,32 @@ intelInitSpanFuncs(GLcontext * ctx)
* Plug in appropriate span read/write functions for the given renderbuffer.
* These are used for the software fallbacks.
*/
void
intel_set_span_functions(struct gl_renderbuffer *rb, enum tiling_mode tiling)
static void
intel_set_span_functions(struct intel_context *intel,
struct gl_renderbuffer *rb)
{
struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
uint32_t tiling;
/* If in GEM mode, we need to do the tile address swizzling ourselves,
* instead of the fence registers handling it.
*/
if (intel->ttm)
tiling = irb->region->tiling;
else
tiling = I915_TILING_NONE;
if (rb->_ActualFormat == GL_RGB5) {
/* 565 RGB */
switch (tiling) {
case INTEL_TILE_NONE:
case I915_TILING_NONE:
default:
intelInitPointers_RGB565(rb);
break;
case INTEL_TILE_X:
case I915_TILING_X:
intel_XTile_InitPointers_RGB565(rb);
break;
case INTEL_TILE_Y:
case I915_TILING_Y:
intel_YTile_InitPointers_RGB565(rb);
break;
}
@@ -701,28 +703,28 @@ intel_set_span_functions(struct gl_renderbuffer *rb, enum tiling_mode tiling)
else if (rb->_ActualFormat == GL_RGBA8) {
/* 8888 RGBA */
switch (tiling) {
case INTEL_TILE_NONE:
case I915_TILING_NONE:
default:
intelInitPointers_ARGB8888(rb);
break;
case INTEL_TILE_X:
case I915_TILING_X:
intel_XTile_InitPointers_ARGB8888(rb);
break;
case INTEL_TILE_Y:
case I915_TILING_Y:
intel_YTile_InitPointers_ARGB8888(rb);
break;
}
}
else if (rb->_ActualFormat == GL_DEPTH_COMPONENT16) {
switch (tiling) {
case INTEL_TILE_NONE:
case I915_TILING_NONE:
default:
intelInitDepthPointers_z16(rb);
break;
case INTEL_TILE_X:
case I915_TILING_X:
intel_XTile_InitDepthPointers_z16(rb);
break;
case INTEL_TILE_Y:
case I915_TILING_Y:
intel_YTile_InitDepthPointers_z16(rb);
break;
}
@@ -730,28 +732,28 @@ intel_set_span_functions(struct gl_renderbuffer *rb, enum tiling_mode tiling)
else if (rb->_ActualFormat == GL_DEPTH_COMPONENT24 || /* XXX FBO remove */
rb->_ActualFormat == GL_DEPTH24_STENCIL8_EXT) {
switch (tiling) {
case INTEL_TILE_NONE:
case I915_TILING_NONE:
default:
intelInitDepthPointers_z24_s8(rb);
break;
case INTEL_TILE_X:
case I915_TILING_X:
intel_XTile_InitDepthPointers_z24_s8(rb);
break;
case INTEL_TILE_Y:
case I915_TILING_Y:
intel_YTile_InitDepthPointers_z24_s8(rb);
break;
}
}
else if (rb->_ActualFormat == GL_STENCIL_INDEX8_EXT) {
switch (tiling) {
case INTEL_TILE_NONE:
case I915_TILING_NONE:
default:
intelInitStencilPointers_z24_s8(rb);
break;
case INTEL_TILE_X:
case I915_TILING_X:
intel_XTile_InitStencilPointers_z24_s8(rb);
break;
case INTEL_TILE_Y:
case I915_TILING_Y:
intel_YTile_InitStencilPointers_z24_s8(rb);
break;
}

3
src/mesa/drivers/dri/intel/intel_span.h
View File

@@ -33,7 +33,4 @@ extern void intelInitSpanFuncs(GLcontext * ctx);
extern void intelSpanRenderFinish(GLcontext * ctx);
extern void intelSpanRenderStart(GLcontext * ctx);
extern void intel_set_span_functions(struct gl_renderbuffer *rb,
enum tiling_mode tiling);
#endif

2
src/mesa/drivers/dri/intel/intel_tex_copy.c
View File

@@ -148,7 +148,7 @@ do_copy_texsubimage(struct intel_context *intel,
intelImage->mt->pitch,
intelImage->mt->region->buffer,
image_offset,
intelImage->mt->region->tiled,
intelImage->mt->region->tiling,
x, y + height, dstx, dsty, width, height,
GL_COPY); /* ? */
}