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iris: Reduce fast-clear post-amble flushes

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On gfx12+, the post-amble flushes contain the stalls necessary to ensure
the prior operation is complete. Remove the extra uses
iris_emit_end_of_pipe_sync().

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31600>
This commit is contained in:
Nanley Chery
2024-10-11 14:27:05 -04:00
committed by Marge Bot
parent 634daf2827
commit 2e7f344508
1 changed files with 44 additions and 7 deletions
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51
src/gallium/drivers/iris/iris_clear.c
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@@ -307,13 +307,50 @@ fast_clear_color(struct iris_context *ice,
box->x, box->y, box->x + box->width,
box->y + box->height);
blorp_batch_finish(&blorp_batch);
iris_emit_end_of_pipe_sync(batch,
"fast clear: post flush",
PIPE_CONTROL_RENDER_TARGET_FLUSH |
(devinfo->verx10 == 120 ?
PIPE_CONTROL_TILE_CACHE_FLUSH |
PIPE_CONTROL_DEPTH_STALL : 0) |
PIPE_CONTROL_PSS_STALL_SYNC);
if (devinfo->verx10 >= 125) {
/* From the ACM PRM Vol. 9, "Color Fast Clear Synchronization":
*
* Postamble post fast clear synchronization
*
* PIPE_CONTROL:
* PS sync stall = 1
* RT flush = 1
*/
iris_emit_pipe_control_flush(batch, "fast clear: post flush",
PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_PSS_STALL_SYNC);
} else if (devinfo->verx10 == 120) {
/* From the TGL PRM Vol. 9, "Color Fast Clear Synchronization":
*
* Postamble post fast clear synchronization
*
* PIPE_CONTROL:
* Depth Stall = 1
* Tile Cache Flush = 1
* RT Write Flush = 1
*/
iris_emit_pipe_control_flush(batch, "fast clear: post flush",
PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_TILE_CACHE_FLUSH |
PIPE_CONTROL_RENDER_TARGET_FLUSH);
} else {
/* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
*
* After Render target fast clear, pipe-control with color cache
* write-flush must be issued before sending any DRAW commands on
* that render target.
*
* From the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
*
* Any transition from any value in {Clear, Render, Resolve} to a
* different value in {Clear, Render, Resolve} requires end of pipe
* synchronization.
*/
iris_emit_end_of_pipe_sync(batch, "fast clear: post flush",
PIPE_CONTROL_RENDER_TARGET_FLUSH);
}
iris_batch_sync_region_end(batch);
iris_resource_set_aux_state(ice, res, level, box->z,