r300g: fix mipmapped 3D textures
This is a bug in the CS checker causing CS being rejected.
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@@ -759,6 +759,29 @@ static unsigned r300_texture_get_nblocksy(struct r300_texture* tex,
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return util_format_get_nblocksy(tex->b.b.format, height);
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return util_format_get_nblocksy(tex->b.b.format, height);
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}
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}
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static void r300_texture_3d_fix_mipmapping(struct r300_screen *screen,
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struct r300_texture *tex)
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{
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/* The kernels <= 2.6.34-rc3 compute the size of mipmapped 3D textures
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* incorrectly. This is a workaround to prevent CS from being rejected. */
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unsigned i, size;
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if (screen->rws->get_value(screen->rws, R300_VID_TEX3D_MIP_BUG) &&
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tex->b.b.target == PIPE_TEXTURE_3D &&
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tex->b.b.last_level > 0) {
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size = 0;
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for (i = 0; i <= tex->b.b.last_level; i++) {
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size += r300_texture_get_stride(screen, tex, i) *
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r300_texture_get_nblocksy(tex, i);
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}
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size *= tex->b.b.depth0;
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tex->size = size;
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}
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}
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static void r300_setup_miptree(struct r300_screen* screen,
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static void r300_setup_miptree(struct r300_screen* screen,
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struct r300_texture* tex)
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struct r300_texture* tex)
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{
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{
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@@ -930,6 +953,7 @@ struct pipe_resource* r300_texture_create(struct pipe_screen* screen,
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r300_setup_tiling(screen, tex);
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r300_setup_tiling(screen, tex);
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}
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}
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r300_setup_miptree(rscreen, tex);
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r300_setup_miptree(rscreen, tex);
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r300_texture_3d_fix_mipmapping(rscreen, tex);
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r300_texture_setup_immutable_state(rscreen, tex);
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r300_texture_setup_immutable_state(rscreen, tex);
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r300_texture_setup_fb_state(rscreen, tex);
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r300_texture_setup_fb_state(rscreen, tex);
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@@ -50,7 +50,8 @@ enum r300_value_id {
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R300_VID_PCI_ID,
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R300_VID_PCI_ID,
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R300_VID_GB_PIPES,
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R300_VID_GB_PIPES,
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R300_VID_Z_PIPES,
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R300_VID_Z_PIPES,
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R300_VID_SQUARE_TILING_SUPPORT
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R300_VID_SQUARE_TILING_SUPPORT,
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R300_VID_TEX3D_MIP_BUG,
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};
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};
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struct r300_winsys_screen {
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struct r300_winsys_screen {
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@@ -100,6 +100,9 @@ static void do_ioctls(int fd, struct radeon_libdrm_winsys* winsys)
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version->version_minor >= 1;
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version->version_minor >= 1;
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#endif
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#endif
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/* XXX */
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winsys->tex3d_mip_bug = TRUE;
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info.request = RADEON_INFO_DEVICE_ID;
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info.request = RADEON_INFO_DEVICE_ID;
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retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
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retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
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if (retval) {
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if (retval) {
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@@ -264,6 +264,8 @@ static uint32_t radeon_get_value(struct r300_winsys_screen *rws,
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return ws->z_pipes;
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return ws->z_pipes;
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case R300_VID_SQUARE_TILING_SUPPORT:
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case R300_VID_SQUARE_TILING_SUPPORT:
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return ws->squaretiling;
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return ws->squaretiling;
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case R300_VID_TEX3D_MIP_BUG:
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return ws->tex3d_mip_bug;
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}
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}
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return 0;
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return 0;
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}
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}
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@@ -60,6 +60,9 @@ struct radeon_libdrm_winsys {
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/* Square tiling support. */
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/* Square tiling support. */
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boolean squaretiling;
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boolean squaretiling;
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/* Square tiling support. */
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boolean tex3d_mip_bug;
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/* DRM FD */
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/* DRM FD */
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int fd;
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int fd;
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