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intel/eu: SVB writes only happen on Gen6

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It's a Gen6 XFB thing.  It's never used for anything else so there's no
point in having a target cache switch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
This commit is contained in:
Jason Ekstrand
2021-02-05 08:09:47 -06:00
committed by Marge Bot
parent 0421690f83
commit 2e7656ae2f
1 changed files with 2 additions and 4 deletions
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6
src/intel/compiler/brw_eu_emit.c
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@@ -3067,10 +3067,8 @@ brw_svb_write(struct brw_codegen *p,
bool send_commit_msg)
{
const struct intel_device_info *devinfo = p->devinfo;
const unsigned target_cache =
(devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE :
devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE :
BRW_SFID_DATAPORT_WRITE);
assert(devinfo->ver == 6);
const unsigned target_cache = GFX6_SFID_DATAPORT_RENDER_CACHE;
brw_inst *insn;
gfx6_resolve_implied_move(p, &src0, msg_reg_nr);