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intel/blorp: Take an isl_swizzle instead of a SWIZZLE

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Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Jason Ekstrand
2016-08-27 21:48:40 -07:00
parent 7ddb21708c
commit 2dba5489ae
3 changed files with 30 additions and 29 deletions
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2
src/intel/blorp/blorp.h
View File

@@ -98,7 +98,7 @@ void
blorp_blit(struct blorp_batch *batch,
const struct blorp_surf *src_surf,
unsigned src_level, unsigned src_layer,
enum isl_format src_format, int src_swizzle,
enum isl_format src_format, struct isl_swizzle src_swizzle,
const struct blorp_surf *dst_surf,
unsigned dst_level, unsigned dst_layer,
enum isl_format dst_format,

29
src/intel/blorp/blorp_blit.c
View File

@@ -21,7 +21,6 @@
* IN THE SOFTWARE.
*/
#include "program/prog_instruction.h"
#include "compiler/nir/nir_builder.h"
#include "blorp_priv.h"
@@ -1248,25 +1247,6 @@ brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform *xform,
}
}
/**
* Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
* "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
*
* SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
* 0 1 2 3 4 5
* 4 5 6 7 0 1
* SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
*
* which is simply adding 4 then modding by 8 (or anding with 7).
*
* We then may need to apply workarounds for textureGather hardware bugs.
*/
static enum isl_channel_select
swizzle_to_scs(GLenum swizzle)
{
return (enum isl_channel_select)((swizzle + 4) & 7);
}
static void
surf_convert_to_single_slice(const struct isl_device *isl_dev,
struct brw_blorp_surface_info *info)
@@ -1380,7 +1360,7 @@ void
blorp_blit(struct blorp_batch *batch,
const struct blorp_surf *src_surf,
unsigned src_level, unsigned src_layer,
enum isl_format src_format, int src_swizzle,
enum isl_format src_format, struct isl_swizzle src_swizzle,
const struct blorp_surf *dst_surf,
unsigned dst_level, unsigned dst_layer,
enum isl_format dst_format,
@@ -1637,12 +1617,7 @@ blorp_blit(struct blorp_batch *batch,
brw_blorp_get_blit_kernel(batch->blorp, &params, &wm_prog_key);
params.src.view.swizzle = (struct isl_swizzle) {
.r = swizzle_to_scs(GET_SWZ(src_swizzle, 0)),
.g = swizzle_to_scs(GET_SWZ(src_swizzle, 1)),
.b = swizzle_to_scs(GET_SWZ(src_swizzle, 2)),
.a = swizzle_to_scs(GET_SWZ(src_swizzle, 3)),
};
params.src.view.swizzle = src_swizzle;
batch->blorp->exec(batch, &params);
}

28
src/mesa/drivers/dri/i965/brw_blorp.c
View File

@@ -255,6 +255,25 @@ brw_blorp_to_isl_format(struct brw_context *brw, mesa_format format,
}
}
/**
* Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
* "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
*
* SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
* 0 1 2 3 4 5
* 4 5 6 7 0 1
* SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
*
* which is simply adding 4 then modding by 8 (or anding with 7).
*
* We then may need to apply workarounds for textureGather hardware bugs.
*/
static enum isl_channel_select
swizzle_to_scs(GLenum swizzle)
{
return (enum isl_channel_select)((swizzle + 4) & 7);
}
/**
* Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
* INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
@@ -330,10 +349,17 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
blorp_surf_for_miptree(brw, &dst_surf, dst_mt, true,
&dst_level, &tmp_surfs[2]);
struct isl_swizzle src_isl_swizzle = {
.r = swizzle_to_scs(GET_SWZ(src_swizzle, 0)),
.g = swizzle_to_scs(GET_SWZ(src_swizzle, 1)),
.b = swizzle_to_scs(GET_SWZ(src_swizzle, 2)),
.a = swizzle_to_scs(GET_SWZ(src_swizzle, 3)),
};
struct blorp_batch batch;
blorp_batch_init(&brw->blorp, &batch, brw);
blorp_blit(&batch, &src_surf, src_level, src_layer,
brw_blorp_to_isl_format(brw, src_format, false), src_swizzle,
brw_blorp_to_isl_format(brw, src_format, false), src_isl_swizzle,
&dst_surf, dst_level, dst_layer,
brw_blorp_to_isl_format(brw, dst_format, true),
src_x0, src_y0, src_x1, src_y1,