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radeonsi: convert gfx10_emit_ge_pc_alloc to radeon_opt_set_uconfig_reg

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Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343>
This commit is contained in:
Marek Olšák
2021-08-18 15:27:47 -04:00
committed by Marge Bot
parent edb5fa4d59
commit 2d8dfb9111
2 changed files with 19 additions and 22 deletions
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10
src/gallium/drivers/radeonsi/si_build_pm4.h
View File

@@ -269,6 +269,16 @@
} \ } \
} while (0) } while (0)
#define radeon_opt_set_uconfig_reg(sctx, offset, reg, val) do { \
unsigned __value = val; \
if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x1) != 0x1 || \
sctx->tracked_regs.reg_value[reg] != __value) { \
radeon_set_uconfig_reg(cs, offset, __value); \
sctx->tracked_regs.reg_saved |= 0x1ull << (reg); \
sctx->tracked_regs.reg_value[reg] = __value; \
} \
} while (0)
#define radeon_set_privileged_config_reg(cs, reg, value) do { \ #define radeon_set_privileged_config_reg(cs, reg, value) do { \
assert((reg) < CIK_UCONFIG_REG_OFFSET); \ assert((reg) < CIK_UCONFIG_REG_OFFSET); \
radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); \ radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); \

31
src/gallium/drivers/radeonsi/si_state_shaders.c
View File

@@ -973,23 +973,6 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
} }
} }
static void gfx10_emit_ge_pc_alloc(struct si_context *sctx, unsigned value)
{
enum si_tracked_reg reg = SI_TRACKED_GE_PC_ALLOC;
if (((sctx->tracked_regs.reg_saved >> reg) & 0x1) != 0x1 ||
sctx->tracked_regs.reg_value[reg] != value) {
struct radeon_cmdbuf *cs = &sctx->gfx_cs;
radeon_begin(cs);
radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC, value);
radeon_end();
sctx->tracked_regs.reg_saved |= 0x1ull << reg;
sctx->tracked_regs.reg_value[reg] = value;
}
}
bool gfx10_is_ngg_passthrough(struct si_shader *shader) bool gfx10_is_ngg_passthrough(struct si_shader *shader)
{ {
struct si_shader_selector *sel = shader->selector; struct si_shader_selector *sel = shader->selector;
@@ -1038,10 +1021,10 @@ static void gfx10_emit_shader_ngg_tail(struct si_context *sctx, struct si_shader
SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK); SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
radeon_end_update_context_roll(sctx); radeon_end_update_context_roll(sctx);
/* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */ /* These don't cause a context roll. */
gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.ngg.ge_pc_alloc);
radeon_begin_again(&sctx->gfx_cs); radeon_begin_again(&sctx->gfx_cs);
radeon_opt_set_uconfig_reg(sctx, R_030980_GE_PC_ALLOC, SI_TRACKED_GE_PC_ALLOC,
shader->ctx_reg.ngg.ge_pc_alloc);
radeon_opt_set_sh_reg(sctx, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, radeon_opt_set_sh_reg(sctx, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS, SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
shader->ctx_reg.ngg.spi_shader_pgm_rsrc3_gs); shader->ctx_reg.ngg.spi_shader_pgm_rsrc3_gs);
@@ -1413,8 +1396,12 @@ static void si_emit_shader_vs(struct si_context *sctx)
radeon_end_update_context_roll(sctx); radeon_end_update_context_roll(sctx);
/* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */ /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
if (sctx->chip_class >= GFX10) if (sctx->chip_class >= GFX10) {
gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.vs.ge_pc_alloc); radeon_begin_again(&sctx->gfx_cs);
radeon_opt_set_uconfig_reg(sctx, R_030980_GE_PC_ALLOC, SI_TRACKED_GE_PC_ALLOC,
shader->ctx_reg.vs.ge_pc_alloc);
radeon_end();
}
} }
/** /**