radv: add llvm_compiler_shader() helper
To match aco_compile_shader(). Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4163> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4163>
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Marge Bot

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4d991c2de4
commit
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@@ -29,6 +29,7 @@
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#include "radv_shader.h"
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#include "radv_shader_helper.h"
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#include "radv_shader_args.h"
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#include "radv_debug.h"
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#include "nir/nir.h"
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#include "sid.h"
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@@ -4266,7 +4267,7 @@ static void ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm,
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free(elf_buffer);
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}
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void
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static void
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radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
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struct radv_shader_binary **rbinary,
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const struct radv_shader_args *args,
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@@ -4392,7 +4393,7 @@ ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
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LLVMPositionBuilderAtEnd(ctx->ac.builder, end_bb);
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}
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void
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static void
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radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
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struct nir_shader *geom_shader,
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struct radv_shader_binary **rbinary,
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@@ -4431,3 +4432,36 @@ radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
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(*rbinary)->is_gs_copy_shader = true;
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}
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void
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llvm_compile_shader(struct radv_device *device,
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unsigned shader_count,
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struct nir_shader *const *shaders,
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struct radv_shader_binary **binary,
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struct radv_shader_args *args)
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{
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enum ac_target_machine_options tm_options = 0;
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struct ac_llvm_compiler ac_llvm;
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bool thread_compiler;
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tm_options |= AC_TM_SUPPORTS_SPILL;
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if (args->options->check_ir)
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tm_options |= AC_TM_CHECK_IR;
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if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
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tm_options |= AC_TM_NO_LOAD_STORE_OPT;
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thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
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radv_init_llvm_compiler(&ac_llvm, thread_compiler,
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args->options->family, tm_options,
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args->shader_info->wave_size);
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if (args->is_gs_copy_shader) {
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radv_compile_gs_copy_shader(&ac_llvm, *shaders, binary, args);
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} else {
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radv_compile_nir_shader(&ac_llvm, binary, args,
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shaders, shader_count);
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}
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radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
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}
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@@ -2361,16 +2361,11 @@ struct radv_fence {
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/* radv_nir_to_llvm.c */
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struct radv_shader_args;
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void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
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struct nir_shader *geom_shader,
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struct radv_shader_binary **rbinary,
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const struct radv_shader_args *args);
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void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
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struct radv_shader_binary **rbinary,
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const struct radv_shader_args *args,
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struct nir_shader *const *nir,
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int nir_count);
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void llvm_compile_shader(struct radv_device *device,
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unsigned shader_count,
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struct nir_shader *const *shaders,
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struct radv_shader_binary **binary,
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struct radv_shader_args *args);
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unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
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gl_shader_stage stage,
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@@ -1119,37 +1119,12 @@ shader_variant_compile(struct radv_device *device,
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if (device->physical_device->use_aco) {
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aco_compile_shader(shader_count, shaders, &binary, &args);
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binary->info = *info;
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} else {
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enum ac_target_machine_options tm_options = 0;
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struct ac_llvm_compiler ac_llvm;
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bool thread_compiler;
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tm_options |= AC_TM_SUPPORTS_SPILL;
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if (options->check_ir)
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tm_options |= AC_TM_CHECK_IR;
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if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
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tm_options |= AC_TM_NO_LOAD_STORE_OPT;
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thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
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radv_init_llvm_compiler(&ac_llvm,
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thread_compiler,
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chip_family, tm_options,
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info->wave_size);
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if (gs_copy_shader) {
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assert(shader_count == 1);
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radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
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&args);
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} else {
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radv_compile_nir_shader(&ac_llvm, &binary, &args,
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shaders, shader_count);
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}
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binary->info = *info;
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radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
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llvm_compile_shader(device, shader_count, shaders, &binary, &args);
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}
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binary->info = *info;
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struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
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keep_shader_info);
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if (!variant) {
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