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intel/compiler: Drop variable group size lowering

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This backend lowering code has been dead since the removal of i965 -
nothing in the current source tree ever sets the flag.

This is handled by iris_setup_uniforms() and crocus_setup_uniforms().
Variable group size does not appear to be a feature in anv.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18055>
This commit is contained in:
Kenneth Graunke
2022-08-15 00:18:59 -07:00
committed by Marge Bot
parent 79f47249e8
commit 2cea0d6ef6
4 changed files with 5 additions and 30 deletions
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6
src/intel/compiler/brw_compiler.h
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@@ -105,12 +105,6 @@ struct brw_compiler {
*/
bool supports_shader_constants;
/**
* Whether or not the driver wants variable group size to be lowered by the
* back-end compiler.
*/
bool lower_variable_group_size;
/**
* Whether indirect UBO loads should use the sampler or go through the
* data/constant cache. For the sampler, UBO surface states have to be set

2
src/intel/compiler/brw_fs.cpp
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@@ -1148,8 +1148,6 @@ fs_visitor::import_uniforms(fs_visitor *v)
this->push_constant_loc = v->push_constant_loc;
this->uniforms = v->uniforms;
this->subgroup_id = v->subgroup_id;
for (unsigned i = 0; i < ARRAY_SIZE(this->group_size); i++)
this->group_size[i] = v->group_size[i];
}
void

1
src/intel/compiler/brw_fs.h
View File

@@ -372,7 +372,6 @@ public:
int *push_constant_loc;
fs_reg subgroup_id;
fs_reg group_size[3];
fs_reg scratch_base;
fs_reg frag_depth;
fs_reg frag_stencil;

26
src/intel/compiler/brw_fs_nir.cpp
View File

@@ -112,21 +112,11 @@ fs_visitor::nir_setup_uniforms()
/* Add uniforms for builtins after regular NIR uniforms. */
assert(uniforms == prog_data->nr_params);
uint32_t *param;
if (nir->info.workgroup_size_variable &&
compiler->lower_variable_group_size) {
param = brw_stage_prog_data_add_params(prog_data, 3);
for (unsigned i = 0; i < 3; i++) {
param[i] = (BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X + i);
group_size[i] = fs_reg(UNIFORM, uniforms++, BRW_REGISTER_TYPE_UD);
}
}
/* Subgroup ID must be the last uniform on the list. This will make
* easier later to split between cross thread and per thread
* uniforms.
*/
param = brw_stage_prog_data_add_params(prog_data, 1);
uint32_t *param = brw_stage_prog_data_add_params(prog_data, 1);
*param = BRW_PARAM_BUILTIN_SUBGROUP_ID;
subgroup_id = fs_reg(UNIFORM, uniforms++, BRW_REGISTER_TYPE_UD);
}
@@ -3976,16 +3966,10 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
}
case nir_intrinsic_load_workgroup_size: {
/* For non-variable case, this should've been lowered already. */
assert(nir->info.workgroup_size_variable);
assert(compiler->lower_variable_group_size);
assert(gl_shader_stage_is_compute(stage));
for (unsigned i = 0; i < 3; i++) {
bld.MOV(retype(offset(dest, bld, i), BRW_REGISTER_TYPE_UD),
group_size[i]);
}
/* Should have been lowered by brw_nir_lower_cs_intrinsics() or
* crocus/iris_setup_uniforms() for the variable group size case.
*/
unreachable("Should have been lowered");
break;
}