intel/compiler: Drop variable group size lowering
This backend lowering code has been dead since the removal of i965 - nothing in the current source tree ever sets the flag. This is handled by iris_setup_uniforms() and crocus_setup_uniforms(). Variable group size does not appear to be a feature in anv. Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18055>
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@@ -105,12 +105,6 @@ struct brw_compiler {
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*/
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*/
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bool supports_shader_constants;
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bool supports_shader_constants;
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/**
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* Whether or not the driver wants variable group size to be lowered by the
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* back-end compiler.
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*/
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bool lower_variable_group_size;
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/**
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/**
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* Whether indirect UBO loads should use the sampler or go through the
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* Whether indirect UBO loads should use the sampler or go through the
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* data/constant cache. For the sampler, UBO surface states have to be set
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* data/constant cache. For the sampler, UBO surface states have to be set
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@@ -1148,8 +1148,6 @@ fs_visitor::import_uniforms(fs_visitor *v)
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this->push_constant_loc = v->push_constant_loc;
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this->push_constant_loc = v->push_constant_loc;
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this->uniforms = v->uniforms;
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this->uniforms = v->uniforms;
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this->subgroup_id = v->subgroup_id;
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this->subgroup_id = v->subgroup_id;
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for (unsigned i = 0; i < ARRAY_SIZE(this->group_size); i++)
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this->group_size[i] = v->group_size[i];
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}
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}
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void
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void
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@@ -372,7 +372,6 @@ public:
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int *push_constant_loc;
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int *push_constant_loc;
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fs_reg subgroup_id;
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fs_reg subgroup_id;
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fs_reg group_size[3];
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fs_reg scratch_base;
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fs_reg scratch_base;
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fs_reg frag_depth;
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fs_reg frag_depth;
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fs_reg frag_stencil;
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fs_reg frag_stencil;
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@@ -112,21 +112,11 @@ fs_visitor::nir_setup_uniforms()
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/* Add uniforms for builtins after regular NIR uniforms. */
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/* Add uniforms for builtins after regular NIR uniforms. */
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assert(uniforms == prog_data->nr_params);
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assert(uniforms == prog_data->nr_params);
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uint32_t *param;
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if (nir->info.workgroup_size_variable &&
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compiler->lower_variable_group_size) {
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param = brw_stage_prog_data_add_params(prog_data, 3);
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for (unsigned i = 0; i < 3; i++) {
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param[i] = (BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X + i);
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group_size[i] = fs_reg(UNIFORM, uniforms++, BRW_REGISTER_TYPE_UD);
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}
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}
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/* Subgroup ID must be the last uniform on the list. This will make
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/* Subgroup ID must be the last uniform on the list. This will make
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* easier later to split between cross thread and per thread
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* easier later to split between cross thread and per thread
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* uniforms.
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* uniforms.
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*/
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*/
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param = brw_stage_prog_data_add_params(prog_data, 1);
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uint32_t *param = brw_stage_prog_data_add_params(prog_data, 1);
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*param = BRW_PARAM_BUILTIN_SUBGROUP_ID;
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*param = BRW_PARAM_BUILTIN_SUBGROUP_ID;
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subgroup_id = fs_reg(UNIFORM, uniforms++, BRW_REGISTER_TYPE_UD);
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subgroup_id = fs_reg(UNIFORM, uniforms++, BRW_REGISTER_TYPE_UD);
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}
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}
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@@ -3976,16 +3966,10 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
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}
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}
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case nir_intrinsic_load_workgroup_size: {
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case nir_intrinsic_load_workgroup_size: {
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/* For non-variable case, this should've been lowered already. */
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/* Should have been lowered by brw_nir_lower_cs_intrinsics() or
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assert(nir->info.workgroup_size_variable);
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* crocus/iris_setup_uniforms() for the variable group size case.
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*/
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assert(compiler->lower_variable_group_size);
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unreachable("Should have been lowered");
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assert(gl_shader_stage_is_compute(stage));
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for (unsigned i = 0; i < 3; i++) {
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bld.MOV(retype(offset(dest, bld, i), BRW_REGISTER_TYPE_UD),
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group_size[i]);
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}
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break;
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break;
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}
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}
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