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ir3: Fix stg/ldg immediate offset on a7xx

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Don't multiply by 4 twice. While we're here, fix the in-bounds check on
a6xx, since we need to account for the multiplying by 4. This was done
correctly on a7xx but the commit below didn't correctly port it to a6xx
when adding the multiply on a6xx.

Fixes: 01bac643f6 ("freedreno/ir3: Fix ldg/stg offset")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30046>
This commit is contained in:
Connor Abbott
2024-07-04 15:54:56 -04:00
committed by Marge Bot
parent bde26a32e1
commit 2c462fe9cc
1 changed files with 4 additions and 4 deletions
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8
src/freedreno/ir3/ir3_a6xx.c
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@@ -418,17 +418,17 @@ emit_intrinsic_load_global_ir3(struct ir3_context *ctx,
struct ir3_instruction *load;
unsigned shift = ctx->compiler->gen >= 7 ? 2 : 0;
bool const_offset_in_bounds =
nir_src_is_const(intr->src[1]) &&
nir_src_as_int(intr->src[1]) < ((1 << 10) >> shift) &&
nir_src_as_int(intr->src[1]) > -((1 << 10) >> shift);
nir_src_as_int(intr->src[1]) < (1 << 8) &&
nir_src_as_int(intr->src[1]) > -(1 << 8);
if (const_offset_in_bounds) {
load = ir3_LDG(b, addr, 0,
create_immed(b, (nir_src_as_int(intr->src[1]) * 4) << shift),
create_immed(b, nir_src_as_int(intr->src[1]) * 4),
0, create_immed(b, dest_components), 0);
} else {
unsigned shift = ctx->compiler->gen >= 7 ? 2 : 0;
offset = ir3_get_src(ctx, &intr->src[1])[0];
if (shift) {
/* A7XX TODO: Move to NIR for it to be properly optimized? */