OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

radeonsi: enable PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS

Browse Source 
This can remove special handling of tessfactors which also benifit
the nir lower pass which does not handle these as system value.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
This commit is contained in:
Qiang Yu
2022-05-28 18:09:56 +08:00
committed by Marge Bot
parent 7598bfd768
commit 2b7e167bbd
4 changed files with 6 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/amd/llvm/ac_nir_to_llvm.c
View File

@@ -3611,8 +3611,6 @@ static void visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
case nir_intrinsic_load_base_vertex: case nir_intrinsic_load_base_vertex:
case nir_intrinsic_load_first_vertex: case nir_intrinsic_load_first_vertex:
case nir_intrinsic_load_workgroup_size: case nir_intrinsic_load_workgroup_size:
case nir_intrinsic_load_tess_level_outer:
case nir_intrinsic_load_tess_level_inner:
case nir_intrinsic_load_tess_level_outer_default: case nir_intrinsic_load_tess_level_outer_default:
case nir_intrinsic_load_tess_level_inner_default: case nir_intrinsic_load_tess_level_inner_default:
case nir_intrinsic_load_tess_rel_patch_id_amd: case nir_intrinsic_load_tess_rel_patch_id_amd:

1
src/gallium/drivers/radeonsi/si_get.c
View File

@@ -165,6 +165,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_IMAGE_STORE_FORMATTED: case PIPE_CAP_IMAGE_STORE_FORMATTED:
case PIPE_CAP_ALLOW_DRAW_OUT_OF_ORDER: case PIPE_CAP_ALLOW_DRAW_OUT_OF_ORDER:
case PIPE_CAP_QUERY_SO_OVERFLOW: case PIPE_CAP_QUERY_SO_OVERFLOW:
case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
return 1; return 1;
case PIPE_CAP_TEXTURE_TRANSFER_MODES: case PIPE_CAP_TEXTURE_TRANSFER_MODES:

15
src/gallium/drivers/radeonsi/si_shader_info.c
View File

@@ -440,8 +440,6 @@ static void scan_instruction(const struct nir_shader *nir, struct si_shader_info
break; break;
case nir_intrinsic_load_barycentric_at_sample: /* This loads sample positions. */ case nir_intrinsic_load_barycentric_at_sample: /* This loads sample positions. */
case nir_intrinsic_load_tess_level_outer: /* TES input read from memory */
case nir_intrinsic_load_tess_level_inner: /* TES input read from memory */
info->uses_vmem_load_other = true; info->uses_vmem_load_other = true;
break; break;
@@ -625,6 +623,11 @@ void si_nir_scan_shader(struct si_screen *sscreen, const struct nir_shader *nir,
info->tessfactors_are_def_in_all_invocs = are_tessfactors_def_in_all_invocs(nir); info->tessfactors_are_def_in_all_invocs = are_tessfactors_def_in_all_invocs(nir);
} }
/* tess factors are loaded as input instead of system value */
info->reads_tess_factors = nir->info.patch_inputs_read &
(BITFIELD64_BIT(VARYING_SLOT_TESS_LEVEL_INNER) |
BITFIELD64_BIT(VARYING_SLOT_TESS_LEVEL_OUTER));
info->uses_frontface = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRONT_FACE); info->uses_frontface = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRONT_FACE);
info->uses_instanceid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID); info->uses_instanceid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID);
info->uses_base_vertex = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BASE_VERTEX); info->uses_base_vertex = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BASE_VERTEX);
@@ -639,8 +642,6 @@ void si_nir_scan_shader(struct si_screen *sscreen, const struct nir_shader *nir,
info->uses_primid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID) || info->uses_primid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID) ||
nir->info.inputs_read & VARYING_BIT_PRIMITIVE_ID; nir->info.inputs_read & VARYING_BIT_PRIMITIVE_ID;
info->reads_samplemask = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN); info->reads_samplemask = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN);
info->reads_tess_factors = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_TESS_LEVEL_INNER) ||
BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_TESS_LEVEL_OUTER);
info->uses_linear_sample = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE); info->uses_linear_sample = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE);
info->uses_linear_centroid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID); info->uses_linear_centroid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID);
info->uses_linear_center = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL); info->uses_linear_center = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL);
@@ -686,12 +687,6 @@ void si_nir_scan_shader(struct si_screen *sscreen, const struct nir_shader *nir,
info->output_usagemask[info->num_outputs] = 0x1; info->output_usagemask[info->num_outputs] = 0x1;
} }
if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
/* This is a hack to simplify loading tess levels in TES. */
info->input[info->num_inputs].semantic = VARYING_SLOT_TESS_LEVEL_OUTER;
info->input[info->num_inputs + 1].semantic = VARYING_SLOT_TESS_LEVEL_INNER;
}
if (nir->info.stage == MESA_SHADER_FRAGMENT) { if (nir->info.stage == MESA_SHADER_FRAGMENT) {
info->allow_flat_shading = !(info->uses_persp_center || info->uses_persp_centroid || info->allow_flat_shading = !(info->uses_persp_center || info->uses_persp_centroid ||
info->uses_persp_sample || info->uses_linear_center || info->uses_persp_sample || info->uses_linear_center ||

7
src/gallium/drivers/radeonsi/si_shader_llvm.c
View File

@@ -718,7 +718,6 @@ void si_build_wrapper_function(struct si_shader_context *ctx, LLVMValueRef *part
static LLVMValueRef si_llvm_load_intrinsic(struct ac_shader_abi *abi, nir_intrinsic_op op) static LLVMValueRef si_llvm_load_intrinsic(struct ac_shader_abi *abi, nir_intrinsic_op op)
{ {
struct si_shader_context *ctx = si_shader_context_from_abi(abi); struct si_shader_context *ctx = si_shader_context_from_abi(abi);
const struct si_shader_info *info = &ctx->shader->selector->info;
switch (op) { switch (op) {
case nir_intrinsic_load_first_vertex: case nir_intrinsic_load_first_vertex:
@@ -746,12 +745,6 @@ static LLVMValueRef si_llvm_load_intrinsic(struct ac_shader_abi *abi, nir_intrin
return ac_build_gather_values(&ctx->ac, chan, 3); return ac_build_gather_values(&ctx->ac, chan, 3);
} }
case nir_intrinsic_load_tess_level_outer:
return abi->load_tess_varyings(abi, ctx->ac.f32, NULL, NULL, info->num_inputs, 0, 4, true);
case nir_intrinsic_load_tess_level_inner:
return abi->load_tess_varyings(abi, ctx->ac.f32, NULL, NULL, info->num_inputs + 1, 0, 4, true);
case nir_intrinsic_load_tess_level_outer_default: case nir_intrinsic_load_tess_level_outer_default:
case nir_intrinsic_load_tess_level_inner_default: { case nir_intrinsic_load_tess_level_inner_default: {
LLVMValueRef slot = LLVMConstInt(ctx->ac.i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0); LLVMValueRef slot = LLVMConstInt(ctx->ac.i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);