ilo: use BLT engine to copy between textures
Emit XY_SRC_COPY_BLT to do the job. Since ETC1 textures cannot be mapped for reading, as is required by util_copy_resource_region, this fixes copying of ETC1 textures.
This commit is contained in:
Chia-I Wu
@@ -57,6 +57,33 @@ ilo_blit_own_blt_ring(struct ilo_context *ilo)
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ilo_cp_set_owner(ilo->cp, NULL, 0);
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}
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static void
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gen6_MI_FLUSH_DW(struct ilo_context *ilo)
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{
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const uint8_t cmd_len = 4;
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struct ilo_cp *cp = ilo->cp;
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ilo_cp_begin(cp, cmd_len);
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ilo_cp_write(cp, MI_FLUSH_DW | (cmd_len - 2));
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ilo_cp_write(cp, 0);
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ilo_cp_write(cp, 0);
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ilo_cp_write(cp, 0);
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ilo_cp_end(cp);
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}
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static void
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gen6_MI_LOAD_REGISTER_IMM(struct ilo_context *ilo, uint32_t reg, uint32_t val)
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{
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const uint8_t cmd_len = 3;
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struct ilo_cp *cp = ilo->cp;
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ilo_cp_begin(cp, cmd_len);
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ilo_cp_write(cp, MI_LOAD_REGISTER_IMM | (cmd_len - 2));
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ilo_cp_write(cp, reg);
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ilo_cp_write(cp, val);
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ilo_cp_end(cp);
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}
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static void
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gen6_XY_COLOR_BLT(struct ilo_context *ilo, struct intel_bo *dst_bo,
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uint32_t dst_offset, int16_t dst_pitch,
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@@ -174,6 +201,210 @@ gen6_SRC_COPY_BLT(struct ilo_context *ilo, struct intel_bo *dst_bo,
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ilo_cp_end(cp);
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}
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static void
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gen6_XY_SRC_COPY_BLT(struct ilo_context *ilo, struct intel_bo *dst_bo,
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uint32_t dst_offset, int16_t dst_pitch,
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enum intel_tiling_mode dst_tiling,
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int16_t x1, int16_t y1, int16_t x2, int16_t y2,
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struct intel_bo *src_bo,
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uint32_t src_offset, int16_t src_pitch,
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enum intel_tiling_mode src_tiling,
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int16_t src_x, int16_t src_y,
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uint8_t rop, int cpp, bool write_alpha)
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{
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const uint8_t cmd_len = 8;
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struct ilo_cp *cp = ilo->cp;
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int dst_align, dst_pitch_shift;
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int src_align, src_pitch_shift;
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uint32_t dw0, dw1;
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dw0 = XY_SRC_COPY_BLT_CMD | (cmd_len - 2);
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if (dst_tiling == INTEL_TILING_NONE) {
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dst_align = 4;
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dst_pitch_shift = 0;
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}
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else {
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dw0 |= XY_DST_TILED;
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dst_align = (dst_tiling == INTEL_TILING_Y) ? 128 : 512;
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/* in dwords when tiled */
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dst_pitch_shift = 2;
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}
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if (src_tiling == INTEL_TILING_NONE) {
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src_align = 4;
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src_pitch_shift = 0;
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}
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else {
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dw0 |= XY_SRC_TILED;
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src_align = (src_tiling == INTEL_TILING_Y) ? 128 : 512;
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/* in dwords when tiled */
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src_pitch_shift = 2;
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}
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assert(cpp == 4 || cpp == 2 || cpp == 1);
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assert((x2 - x1) * cpp < gen6_max_bytes_per_scanline);
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assert(y2 - y1 < gen6_max_scanlines);
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assert(dst_offset % dst_align == 0 && dst_pitch % dst_align == 0);
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assert(src_offset % src_align == 0 && src_pitch % src_align == 0);
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dw1 = rop << 16 |
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dst_pitch >> dst_pitch_shift;
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switch (cpp) {
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case 4:
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dw0 |= XY_BLT_WRITE_RGB;
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if (write_alpha)
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dw0 |= XY_BLT_WRITE_ALPHA;
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dw1 |= BR13_8888;
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break;
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case 2:
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dw1 |= BR13_565;
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break;
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case 1:
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dw1 |= BR13_8;
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break;
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}
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ilo_cp_begin(cp, cmd_len);
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ilo_cp_write(cp, dw0);
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ilo_cp_write(cp, dw1);
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ilo_cp_write(cp, y1 << 16 | x1);
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ilo_cp_write(cp, y2 << 16 | x2);
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ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_DOMAIN_RENDER,
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INTEL_DOMAIN_RENDER);
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ilo_cp_write(cp, src_y << 16 | src_x);
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ilo_cp_write(cp, src_pitch >> src_pitch_shift);
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ilo_cp_write_bo(cp, src_offset, src_bo, INTEL_DOMAIN_RENDER, 0);
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ilo_cp_end(cp);
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}
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static bool
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tex_copy_region(struct ilo_context *ilo,
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struct ilo_texture *dst,
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unsigned dst_level,
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unsigned dst_x, unsigned dst_y, unsigned dst_z,
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struct ilo_texture *src,
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unsigned src_level,
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const struct pipe_box *src_box)
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{
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const struct util_format_description *desc =
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util_format_description(dst->bo_format);
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const unsigned max_extent = 32767; /* INT16_MAX */
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const uint8_t rop = 0xcc; /* SRCCOPY */
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struct intel_bo *aper_check[3];
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uint32_t swctrl;
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int cpp, xscale, slice;
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/* no W-tiling support */
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if (dst->separate_s8 || src->separate_s8)
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return false;
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if (dst->bo_stride > max_extent || src->bo_stride > max_extent)
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return false;
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cpp = desc->block.bits / 8;
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xscale = 1;
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/* accommodate for larger cpp */
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if (cpp > 4) {
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if (cpp % 2 == 1)
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return false;
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cpp = (cpp % 4 == 0) ? 4 : 2;
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xscale = (desc->block.bits / 8) / cpp;
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}
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ilo_blit_own_blt_ring(ilo);
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/* make room if necessary */
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aper_check[0] = ilo->cp->bo;
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aper_check[1] = dst->bo;
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aper_check[2] = src->bo;
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if (ilo->winsys->check_aperture_space(ilo->winsys, aper_check, 3))
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ilo_cp_flush(ilo->cp);
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swctrl = 0x0;
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if (dst->tiling == INTEL_TILING_Y) {
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swctrl |= BCS_SWCTRL_DST_Y << 16 |
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BCS_SWCTRL_DST_Y;
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}
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if (src->tiling == INTEL_TILING_Y) {
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swctrl |= BCS_SWCTRL_SRC_Y << 16 |
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BCS_SWCTRL_SRC_Y;
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}
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if (swctrl) {
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/*
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* Most clients expect BLT engine to be stateless. If we have to set
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* BCS_SWCTRL to a non-default value, we have to set it back in the same
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* batch buffer.
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*/
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if (ilo_cp_space(ilo->cp) < (4 + 3) * 2 + src_box->depth * 8)
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ilo_cp_flush(ilo->cp);
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ilo_cp_assert_no_implicit_flush(ilo->cp, true);
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/*
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* From the Ivy Bridge PRM, volume 1 part 4, page 133:
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*
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* "SW is required to flush the HW before changing the polarity of
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* this bit (Tile Y Destination/Source)."
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*/
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gen6_MI_FLUSH_DW(ilo);
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gen6_MI_LOAD_REGISTER_IMM(ilo, BCS_SWCTRL, swctrl);
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swctrl &= ~(BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y);
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}
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for (slice = 0; slice < src_box->depth; slice++) {
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const struct ilo_texture_slice *dst_slice =
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&dst->slice_offsets[dst_level][dst_z + slice];
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const struct ilo_texture_slice *src_slice =
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&src->slice_offsets[src_level][src_box->z + slice];
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unsigned x1, y1, x2, y2, src_x, src_y;
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x1 = (dst_slice->x + dst_x) * xscale;
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y1 = dst_slice->y + dst_y;
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x2 = (x1 + src_box->width) * xscale;
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y2 = y1 + src_box->height;
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src_x = (src_slice->x + src_box->x) * xscale;
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src_y = src_slice->y + src_box->y;
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x1 /= desc->block.width;
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y1 /= desc->block.height;
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x2 = (x2 + desc->block.width - 1) / desc->block.width;
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y2 = (y2 + desc->block.height - 1) / desc->block.height;
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src_x /= desc->block.width;
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src_y /= desc->block.height;
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if (x2 > max_extent || y2 > max_extent ||
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src_x > max_extent || src_y > max_extent ||
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(x2 - x1) * cpp > gen6_max_bytes_per_scanline)
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break;
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gen6_XY_SRC_COPY_BLT(ilo,
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dst->bo, 0, dst->bo_stride, dst->tiling,
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x1, y1, x2, y2,
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src->bo, 0, src->bo_stride, src->tiling,
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src_x, src_y, rop, cpp, true);
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}
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if (swctrl) {
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gen6_MI_FLUSH_DW(ilo);
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gen6_MI_LOAD_REGISTER_IMM(ilo, BCS_SWCTRL, swctrl);
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ilo_cp_assert_no_implicit_flush(ilo->cp, false);
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}
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return (slice == src_box->depth);
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}
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static bool
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buf_copy_region(struct ilo_context *ilo,
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struct ilo_buffer *dst, unsigned dst_offset,
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@@ -235,7 +466,12 @@ ilo_resource_copy_region(struct pipe_context *pipe,
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{
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bool success;
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if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
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if (dst->target != PIPE_BUFFER && src->target != PIPE_BUFFER) {
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success = tex_copy_region(ilo_context(pipe),
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ilo_texture(dst), dst_level, dstx, dsty, dstz,
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ilo_texture(src), src_level, src_box);
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}
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else if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
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const unsigned dst_offset = dstx;
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const unsigned src_offset = src_box->x;
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const unsigned size = src_box->width;
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