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radv: switch a bunch of struct/enum to 1.3 versions

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14707>
This commit is contained in:
Samuel Pitoiset
2021-11-19 16:44:26 +01:00
committed by Marge Bot
parent 852197537e
commit 2a88e21570
3 changed files with 25 additions and 25 deletions
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10
src/amd/vulkan/radv_descriptor_set.c
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@@ -726,9 +726,9 @@ radv_CreateDescriptorPool(VkDevice _device, const VkDescriptorPoolCreateInfo *pC
vk_foreach_struct(ext, pCreateInfo->pNext) vk_foreach_struct(ext, pCreateInfo->pNext)
{ {
switch (ext->sType) { switch (ext->sType) {
case VK_STRUCTURE_TYPE_DESCRIPTOR_POOL_INLINE_UNIFORM_BLOCK_CREATE_INFO_EXT: { case VK_STRUCTURE_TYPE_DESCRIPTOR_POOL_INLINE_UNIFORM_BLOCK_CREATE_INFO: {
const VkDescriptorPoolInlineUniformBlockCreateInfoEXT *info = const VkDescriptorPoolInlineUniformBlockCreateInfo *info =
(const VkDescriptorPoolInlineUniformBlockCreateInfoEXT *)ext; (const VkDescriptorPoolInlineUniformBlockCreateInfo *)ext;
/* the sizes are 4 aligned, and we need to align to at /* the sizes are 4 aligned, and we need to align to at
* most 32, which needs at most 28 bytes extra per * most 32, which needs at most 28 bytes extra per
* binding. */ * binding. */
@@ -1019,8 +1019,8 @@ static ALWAYS_INLINE void
write_block_descriptor(struct radv_device *device, struct radv_cmd_buffer *cmd_buffer, void *dst, write_block_descriptor(struct radv_device *device, struct radv_cmd_buffer *cmd_buffer, void *dst,
const VkWriteDescriptorSet *writeset) const VkWriteDescriptorSet *writeset)
{ {
const VkWriteDescriptorSetInlineUniformBlockEXT *inline_ub = const VkWriteDescriptorSetInlineUniformBlock *inline_ub =
vk_find_struct_const(writeset->pNext, WRITE_DESCRIPTOR_SET_INLINE_UNIFORM_BLOCK_EXT); vk_find_struct_const(writeset->pNext, WRITE_DESCRIPTOR_SET_INLINE_UNIFORM_BLOCK);
memcpy(dst, inline_ub->pData, inline_ub->dataSize); memcpy(dst, inline_ub->pData, inline_ub->dataSize);
} }

36
src/amd/vulkan/radv_pipeline.c
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@@ -3385,25 +3385,25 @@ radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
} }
static void static void
radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback) radv_start_feedback(VkPipelineCreationFeedback *feedback)
{ {
if (!feedback) if (!feedback)
return; return;
feedback->duration -= radv_get_current_time(); feedback->duration -= radv_get_current_time();
feedback->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT; feedback->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT;
} }
static void static void
radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit) radv_stop_feedback(VkPipelineCreationFeedback *feedback, bool cache_hit)
{ {
if (!feedback) if (!feedback)
return; return;
feedback->duration += radv_get_current_time(); feedback->duration += radv_get_current_time();
feedback->flags = feedback->flags =
VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT | VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT |
(cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0); (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT : 0);
} }
static bool static bool
@@ -3635,8 +3635,8 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
const struct radv_pipeline_key *pipeline_key, const struct radv_pipeline_key *pipeline_key,
const VkPipelineShaderStageCreateInfo **pStages, const VkPipelineShaderStageCreateInfo **pStages,
const VkPipelineCreateFlags flags, const uint8_t *custom_hash, const VkPipelineCreateFlags flags, const uint8_t *custom_hash,
VkPipelineCreationFeedbackEXT *pipeline_feedback, VkPipelineCreationFeedback *pipeline_feedback,
VkPipelineCreationFeedbackEXT **stage_feedbacks) VkPipelineCreationFeedback **stage_feedbacks)
{ {
struct vk_shader_module fs_m = {0}; struct vk_shader_module fs_m = {0};
struct vk_shader_module *modules[MESA_VULKAN_SHADER_STAGES] = { struct vk_shader_module *modules[MESA_VULKAN_SHADER_STAGES] = {
@@ -3703,9 +3703,9 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
return VK_SUCCESS; return VK_SUCCESS;
} }
if (flags & VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT) { if (flags & VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT) {
radv_stop_feedback(pipeline_feedback, found_in_application_cache); radv_stop_feedback(pipeline_feedback, found_in_application_cache);
return VK_PIPELINE_COMPILE_REQUIRED_EXT; return VK_PIPELINE_COMPILE_REQUIRED;
} }
if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) { if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
@@ -5925,13 +5925,13 @@ radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT); vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
radv_init_feedback(creation_feedback); radv_init_feedback(creation_feedback);
VkPipelineCreationFeedbackEXT *pipeline_feedback = VkPipelineCreationFeedback *pipeline_feedback =
creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL; creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
const VkPipelineShaderStageCreateInfo *pStages[MESA_VULKAN_SHADER_STAGES] = { const VkPipelineShaderStageCreateInfo *pStages[MESA_VULKAN_SHADER_STAGES] = {
0, 0,
}; };
VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_VULKAN_SHADER_STAGES] = {0}; VkPipelineCreationFeedback *stage_feedbacks[MESA_VULKAN_SHADER_STAGES] = {0};
for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) { for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1; gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
pStages[stage] = &pCreateInfo->pStages[i]; pStages[stage] = &pCreateInfo->pStages[i];
@@ -6139,7 +6139,7 @@ radv_CreateGraphicsPipelines(VkDevice _device, VkPipelineCache pipelineCache, ui
result = r; result = r;
pPipelines[i] = VK_NULL_HANDLE; pPipelines[i] = VK_NULL_HANDLE;
if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT) if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT)
break; break;
} }
} }
@@ -6222,15 +6222,15 @@ radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT) if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
key.optimisations_disabled = 1; key.optimisations_disabled = 1;
const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size = const VkPipelineShaderStageRequiredSubgroupSizeCreateInfo *subgroup_size =
vk_find_struct_const(stage->pNext, vk_find_struct_const(stage->pNext,
PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT); PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO);
if (subgroup_size) { if (subgroup_size) {
assert(subgroup_size->requiredSubgroupSize == 32 || assert(subgroup_size->requiredSubgroupSize == 32 ||
subgroup_size->requiredSubgroupSize == 64); subgroup_size->requiredSubgroupSize == 64);
key.cs.compute_subgroup_size = subgroup_size->requiredSubgroupSize; key.cs.compute_subgroup_size = subgroup_size->requiredSubgroupSize;
} else if (stage->flags & VK_PIPELINE_SHADER_STAGE_CREATE_REQUIRE_FULL_SUBGROUPS_BIT_EXT) { } else if (stage->flags & VK_PIPELINE_SHADER_STAGE_CREATE_REQUIRE_FULL_SUBGROUPS_BIT) {
key.cs.require_full_subgroups = true; key.cs.require_full_subgroups = true;
} }
@@ -6250,7 +6250,7 @@ radv_compute_pipeline_create(VkDevice _device, VkPipelineCache _cache,
const VkPipelineShaderStageCreateInfo *pStages[MESA_VULKAN_SHADER_STAGES] = { const VkPipelineShaderStageCreateInfo *pStages[MESA_VULKAN_SHADER_STAGES] = {
0, 0,
}; };
VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_VULKAN_SHADER_STAGES] = {0}; VkPipelineCreationFeedback *stage_feedbacks[MESA_VULKAN_SHADER_STAGES] = {0};
struct radv_pipeline *pipeline; struct radv_pipeline *pipeline;
VkResult result; VkResult result;
@@ -6273,7 +6273,7 @@ radv_compute_pipeline_create(VkDevice _device, VkPipelineCache _cache,
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT); vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
radv_init_feedback(creation_feedback); radv_init_feedback(creation_feedback);
VkPipelineCreationFeedbackEXT *pipeline_feedback = VkPipelineCreationFeedback *pipeline_feedback =
creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL; creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
if (creation_feedback) if (creation_feedback)
stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0]; stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
@@ -6321,7 +6321,7 @@ radv_CreateComputePipelines(VkDevice _device, VkPipelineCache pipelineCache, uin
result = r; result = r;
pPipelines[i] = VK_NULL_HANDLE; pPipelines[i] = VK_NULL_HANDLE;
if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT) if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT)
break; break;
} }
} }

4
src/amd/vulkan/radv_shader.h
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@@ -515,8 +515,8 @@ VkResult radv_create_shaders(struct radv_pipeline *pipeline,
const struct radv_pipeline_key *key, const struct radv_pipeline_key *key,
const VkPipelineShaderStageCreateInfo **pStages, const VkPipelineShaderStageCreateInfo **pStages,
const VkPipelineCreateFlags flags, const uint8_t *custom_hash, const VkPipelineCreateFlags flags, const uint8_t *custom_hash,
VkPipelineCreationFeedbackEXT *pipeline_feedback, VkPipelineCreationFeedback *pipeline_feedback,
VkPipelineCreationFeedbackEXT **stage_feedbacks); VkPipelineCreationFeedback **stage_feedbacks);
struct radv_shader_args; struct radv_shader_args;