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intel/vec4: Remove all support for Gen8+ [v2]

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v2: Restore the gen == 10 hunk in brw_compile_vs (around line 2940).
This function is also used for scalar VS compiles.  Squash in:

    intel/vec4: Reindent after removing Gen8+ support
    intel/vec4: Silence unused parameter warning in try_immediate_source

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> [v1]
Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6826>
This commit is contained in:
Ian Romanick
2020-09-22 13:09:56 -07:00
parent 60e1d0f028
commit 2a49007411
8 changed files with 86 additions and 284 deletions
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76
src/intel/compiler/brw_vec4_visitor.cpp
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@@ -305,23 +305,10 @@ vec4_visitor::fix_3src_operand(const src_reg &src)
return src_reg(expanded);
}
src_reg
vec4_visitor::resolve_source_modifiers(const src_reg &src)
{
if (!src.abs && !src.negate)
return src;
dst_reg resolved = dst_reg(this, glsl_type::ivec4_type);
resolved.type = src.type;
emit(MOV(resolved, src));
return src_reg(resolved);
}
src_reg
vec4_visitor::fix_math_operand(const src_reg &src)
{
if (devinfo->gen < 6 || devinfo->gen >= 8 || src.file == BAD_FILE)
if (devinfo->gen < 6 || src.file == BAD_FILE)
return src;
/* The gen6 math instruction ignores the source modifiers --
@@ -753,35 +740,7 @@ vec4_visitor::emit_pull_constant_load_reg(dst_reg dst,
vec4_instruction *pull;
if (devinfo->gen >= 9) {
/* Gen9+ needs a message header in order to use SIMD4x2 mode */
src_reg header(this, glsl_type::uvec4_type, 2);
pull = new(mem_ctx)
vec4_instruction(VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,
dst_reg(header));
if (before_inst)
emit_before(before_block, before_inst, pull);
else
emit(pull);
dst_reg index_reg = retype(byte_offset(dst_reg(header), REG_SIZE),
offset_reg.type);
pull = MOV(writemask(index_reg, WRITEMASK_X), offset_reg);
if (before_inst)
emit_before(before_block, before_inst, pull);
else
emit(pull);
pull = new(mem_ctx) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
dst,
surf_index,
header);
pull->mlen = 2;
pull->header_size = 1;
} else if (devinfo->gen >= 7) {
if (devinfo->gen >= 7) {
dst_reg grf_offset = dst_reg(this, glsl_type::uint_type);
grf_offset.type = offset_reg.type;
@@ -838,24 +797,9 @@ vec4_visitor::emit_mcs_fetch(const glsl_type *coordinate_type,
inst->base_mrf = 2;
inst->src[1] = surface;
inst->src[2] = brw_imm_ud(0); /* sampler */
inst->mlen = 1;
int param_base;
if (devinfo->gen >= 9) {
/* Gen9+ needs a message header in order to use SIMD4x2 mode */
vec4_instruction *header_inst = new(mem_ctx)
vec4_instruction(VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,
dst_reg(MRF, inst->base_mrf));
emit(header_inst);
inst->mlen = 2;
inst->header_size = 1;
param_base = inst->base_mrf + 1;
} else {
inst->mlen = 1;
param_base = inst->base_mrf;
}
const int param_base = inst->base_mrf;
/* parameters are: u, v, r, lod; lod will always be zero due to api restrictions */
int coord_mask = (1 << coordinate_type->vector_elements) - 1;
@@ -874,7 +818,7 @@ vec4_visitor::emit_mcs_fetch(const glsl_type *coordinate_type,
bool
vec4_visitor::is_high_sampler(src_reg sampler)
{
if (devinfo->gen < 8 && !devinfo->is_haswell)
if (!devinfo->is_haswell)
return false;
return sampler.file != IMM || sampler.ud >= 16;
@@ -902,8 +846,7 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
case ir_txl: opcode = SHADER_OPCODE_TXL; break;
case ir_txd: opcode = SHADER_OPCODE_TXD; break;
case ir_txf: opcode = SHADER_OPCODE_TXF; break;
case ir_txf_ms: opcode = (devinfo->gen >= 9 ? SHADER_OPCODE_TXF_CMS_W :
SHADER_OPCODE_TXF_CMS); break;
case ir_txf_ms: opcode = SHADER_OPCODE_TXF_CMS; break;
case ir_txs: opcode = SHADER_OPCODE_TXS; break;
case ir_tg4: opcode = offset_value.file != BAD_FILE
? SHADER_OPCODE_TG4_OFFSET : SHADER_OPCODE_TG4; break;
@@ -937,7 +880,7 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
* - Sampleinfo message - takes no parameters, but mlen = 0 is illegal
*/
inst->header_size =
(devinfo->gen < 5 || devinfo->gen >= 9 ||
(devinfo->gen < 5 ||
inst->offset != 0 || op == ir_tg4 ||
op == ir_texture_samples ||
is_high_sampler(sampler_reg)) ? 1 : 0;
@@ -1705,11 +1648,6 @@ vec4_visitor::emit_pull_constant_load(bblock_t *block, vec4_instruction *inst,
offset = src_reg(this, glsl_type::uint_type);
emit_before(block, inst, ADD(dst_reg(offset), indirect,
brw_imm_ud(reg_offset * 16)));
} else if (devinfo->gen >= 8) {
/* Store the offset in a GRF so we can send-from-GRF. */
offset = src_reg(this, glsl_type::uint_type);
emit_before(block, inst, MOV(dst_reg(offset),
brw_imm_ud(reg_offset * 16)));
} else {
offset = brw_imm_d(reg_offset * 16);
}