tu: Support VK_EXT_fragment_density_map on a750
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29938>
This commit is contained in:
@@ -1090,9 +1090,14 @@ tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
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}
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/* Make the CP wait until the CP_MEM_WRITE's to the command buffers
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* land.
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* land. When loading FS params via UBOs, we also need to invalidate
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* UCHE because the FS param patchpoint is read through UCHE.
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*/
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tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
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if (cmd->device->compiler->load_shader_consts_via_preamble) {
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tu_emit_event_write<CHIP>(cmd, cs, FD_CACHE_INVALIDATE);
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tu_cs_emit_wfi(cs);
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}
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tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
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}
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}
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@@ -5117,6 +5122,38 @@ fdm_apply_fs_params(struct tu_cmd_buffer *cmd,
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}
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}
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static void
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tu_emit_fdm_params(struct tu_cmd_buffer *cmd,
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struct tu_cs *cs, struct tu_shader *fs,
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unsigned num_units)
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{
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STATIC_ASSERT(IR3_DP_FS_FRAG_INVOCATION_COUNT == IR3_DP_FS_DYNAMIC);
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tu_cs_emit(cs, fs->fs.per_samp ?
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cmd->vk.dynamic_graphics_state.ms.rasterization_samples : 1);
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tu_cs_emit(cs, 0);
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tu_cs_emit(cs, 0);
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tu_cs_emit(cs, 0);
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STATIC_ASSERT(IR3_DP_FS_FRAG_SIZE == IR3_DP_FS_DYNAMIC + 4);
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STATIC_ASSERT(IR3_DP_FS_FRAG_OFFSET == IR3_DP_FS_DYNAMIC + 6);
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if (num_units > 1) {
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if (fs->fs.has_fdm) {
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struct apply_fs_params_state state = {
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.num_consts = num_units - 1,
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};
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tu_create_fdm_bin_patchpoint(cmd, cs, 4 * (num_units - 1),
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fdm_apply_fs_params, state);
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} else {
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for (unsigned i = 1; i < num_units; i++) {
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tu_cs_emit(cs, 1);
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tu_cs_emit(cs, 1);
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tu_cs_emit(cs, fui(0.0f));
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tu_cs_emit(cs, fui(0.0f));
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}
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}
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}
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}
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static void
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tu6_emit_fs_params(struct tu_cmd_buffer *cmd)
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{
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@@ -5151,31 +5188,7 @@ tu6_emit_fs_params(struct tu_cmd_buffer *cmd)
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tu_cs_emit(&cs, 0);
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tu_cs_emit(&cs, 0);
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STATIC_ASSERT(IR3_DP_FS_FRAG_INVOCATION_COUNT == IR3_DP_FS_DYNAMIC);
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tu_cs_emit(&cs, fs->fs.per_samp ?
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cmd->vk.dynamic_graphics_state.ms.rasterization_samples : 1);
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tu_cs_emit(&cs, 0);
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tu_cs_emit(&cs, 0);
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tu_cs_emit(&cs, 0);
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STATIC_ASSERT(IR3_DP_FS_FRAG_SIZE == IR3_DP_FS_DYNAMIC + 4);
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STATIC_ASSERT(IR3_DP_FS_FRAG_OFFSET == IR3_DP_FS_DYNAMIC + 6);
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if (num_units > 1) {
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if (fs->fs.has_fdm) {
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struct apply_fs_params_state state = {
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.num_consts = num_units - 1,
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};
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tu_create_fdm_bin_patchpoint(cmd, &cs, 4 * (num_units - 1),
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fdm_apply_fs_params, state);
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} else {
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for (unsigned i = 1; i < num_units; i++) {
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tu_cs_emit(&cs, 1);
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tu_cs_emit(&cs, 1);
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tu_cs_emit(&cs, fui(0.0f));
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tu_cs_emit(&cs, fui(0.0f));
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}
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}
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}
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tu_emit_fdm_params(cmd, &cs, fs, num_units);
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cmd->state.fs_params = tu_cs_end_draw_state(&cmd->sub_cs, &cs);
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@@ -5183,6 +5196,69 @@ tu6_emit_fs_params(struct tu_cmd_buffer *cmd)
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tu_cs_set_writeable(&cmd->sub_cs, false);
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}
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static void
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tu7_emit_fs_params(struct tu_cmd_buffer *cmd)
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{
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struct tu_shader *fs = cmd->state.shaders[MESA_SHADER_FRAGMENT];
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int ubo_offset = fs->const_state.fdm_ubo.idx;
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if (ubo_offset < 0) {
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cmd->state.fs_params = (struct tu_draw_state) {};
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return;
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}
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unsigned num_units = DIV_ROUND_UP(fs->const_state.fdm_ubo.size, 4);
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if (fs->fs.has_fdm)
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tu_cs_set_writeable(&cmd->sub_cs, true);
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struct tu_cs cs;
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VkResult result =
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tu_cs_begin_sub_stream_aligned(&cmd->sub_cs, num_units, 4, &cs);
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if (result != VK_SUCCESS) {
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tu_cs_set_writeable(&cmd->sub_cs, false);
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vk_command_buffer_set_error(&cmd->vk, result);
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return;
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}
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tu_emit_fdm_params(cmd, &cs, fs, num_units);
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struct tu_draw_state fdm_ubo = tu_cs_end_draw_state(&cmd->sub_cs, &cs);
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if (fs->fs.has_fdm)
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tu_cs_set_writeable(&cmd->sub_cs, false);
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result = tu_cs_begin_sub_stream(&cmd->sub_cs, 6, &cs);
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if (result != VK_SUCCESS) {
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vk_command_buffer_set_error(&cmd->vk, result);
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return;
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}
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tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_FRAG, 5);
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tu_cs_emit(&cs,
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CP_LOAD_STATE6_0_DST_OFF(ubo_offset) |
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CP_LOAD_STATE6_0_STATE_TYPE(ST6_UBO)|
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CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
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CP_LOAD_STATE6_0_STATE_BLOCK(SB6_FS_SHADER) |
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CP_LOAD_STATE6_0_NUM_UNIT(1));
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tu_cs_emit(&cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
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tu_cs_emit(&cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
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tu_cs_emit_qw(&cs,
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fdm_ubo.iova |
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(uint64_t)A6XX_UBO_1_SIZE(num_units) << 32);
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cmd->state.fs_params = tu_cs_end_draw_state(&cmd->sub_cs, &cs);
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}
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static void
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tu_emit_fs_params(struct tu_cmd_buffer *cmd)
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{
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if (cmd->device->compiler->load_shader_consts_via_preamble)
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tu7_emit_fs_params(cmd);
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else
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tu6_emit_fs_params(cmd);
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}
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template <chip CHIP>
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static VkResult
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tu6_draw_common(struct tu_cmd_buffer *cmd,
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@@ -5352,7 +5428,7 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
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if (BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
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MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES) ||
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(cmd->state.dirty & (TU_CMD_DIRTY_PROGRAM | TU_CMD_DIRTY_FDM))) {
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tu6_emit_fs_params(cmd);
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tu_emit_fs_params(cmd);
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dirty_fs_params = true;
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}
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@@ -242,7 +242,7 @@ get_device_extensions(const struct tu_physical_device *device,
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.EXT_extended_dynamic_state3 = true,
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.EXT_external_memory_dma_buf = true,
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.EXT_filter_cubic = device->info->a6xx.has_tex_filter_cubic,
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.EXT_fragment_density_map = !device->info->a7xx.load_shader_consts_via_preamble,
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.EXT_fragment_density_map = true,
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.EXT_global_priority = true,
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.EXT_global_priority_query = true,
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.EXT_graphics_pipeline_library = true,
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@@ -477,10 +477,12 @@ lower_intrinsic(nir_builder *b, nir_intrinsic_instr *instr,
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instr->intrinsic == nir_intrinsic_load_frag_size_ir3 ?
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IR3_DP_FS_FRAG_SIZE : IR3_DP_FS_FRAG_OFFSET;
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unsigned offset = param - IR3_DP_FS_DYNAMIC;
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nir_def *view = instr->src[0].ssa;
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nir_def *result =
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ir3_load_driver_ubo_indirect(b, 2, &shader->const_state.fdm_ubo,
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param, view, nir_intrinsic_range(instr));
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offset, view, nir_intrinsic_range(instr));
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nir_def_replace(&instr->def, result);
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return true;
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@@ -491,7 +493,8 @@ lower_intrinsic(nir_builder *b, nir_intrinsic_instr *instr,
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nir_def *result =
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ir3_load_driver_ubo(b, 1, &shader->const_state.fdm_ubo,
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IR3_DP_FS_FRAG_INVOCATION_COUNT);
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IR3_DP_FS_FRAG_INVOCATION_COUNT -
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IR3_DP_FS_DYNAMIC);
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nir_def_replace(&instr->def, result);
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return true;
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