nir/lower_tex: Add a way to lower TXS(non-0-LOD) instructions
The V3D driver has an open-coded solution for this, and we need the same thing for Panfrost, so let's add a generic way to lower TXS(LOD) into max(TXS(0) >> LOD, 1). Changes in v2: * Use == 0 instead of ! * Rework the minification logic as suggested by Jason * Assign cursor pos at the beginning of the function * Patch the LOD just after retrieving the old value Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
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committed by
Alyssa Rosenzweig

parent
0e489fd360
commit
296c5fd25d
@@ -3426,6 +3426,12 @@ typedef struct nir_lower_tex_options {
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*/
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*/
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bool lower_txd_clamp_if_sampler_index_not_lt_16;
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bool lower_txd_clamp_if_sampler_index_not_lt_16;
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/**
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* If true, lower nir_texop_txs with a non-0-lod into nir_texop_txs with
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* 0-lod followed by a nir_ishr.
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*/
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bool lower_txs_lod;
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/**
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/**
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* If true, apply a .bagr swizzle on tg4 results to handle Broadcom's
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* If true, apply a .bagr swizzle on tg4 results to handle Broadcom's
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* mixed-up tg4 locations.
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* mixed-up tg4 locations.
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@@ -982,6 +982,47 @@ lower_tg4_offsets(nir_builder *b, nir_tex_instr *tex)
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return true;
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return true;
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}
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}
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static bool
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nir_lower_txs_lod(nir_builder *b, nir_tex_instr *tex)
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{
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int lod_idx = nir_tex_instr_src_index(tex, nir_tex_src_lod);
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if (lod_idx < 0 ||
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(nir_src_is_const(tex->src[lod_idx].src) &&
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nir_src_as_int(tex->src[lod_idx].src) == 0))
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return false;
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unsigned dest_size = nir_tex_instr_dest_size(tex);
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b->cursor = nir_before_instr(&tex->instr);
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nir_ssa_def *lod = nir_ssa_for_src(b, tex->src[lod_idx].src, 1);
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/* Replace the non-0-LOD in the initial TXS operation by a 0-LOD. */
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nir_instr_rewrite_src(&tex->instr, &tex->src[lod_idx].src,
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nir_src_for_ssa(nir_imm_int(b, 0)));
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/* TXS(LOD) = max(TXS(0) >> LOD, 1) */
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b->cursor = nir_after_instr(&tex->instr);
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nir_ssa_def *minified = nir_imax(b, nir_ushr(b, &tex->dest.ssa, lod),
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nir_imm_int(b, 1));
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/* Make sure the component encoding the array size (if any) is not
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* minified.
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*/
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if (tex->is_array) {
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nir_ssa_def *comp[3];
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for (unsigned i = 0; i < dest_size - 1; i++)
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comp[i] = nir_channel(b, minified, i);
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comp[dest_size - 1] = nir_channel(b, &tex->dest.ssa, dest_size - 1);
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minified = nir_vec(b, comp, dest_size);
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}
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nir_ssa_def_rewrite_uses_after(&tex->dest.ssa, nir_src_for_ssa(minified),
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minified->parent_instr);
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return true;
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}
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static bool
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static bool
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nir_lower_tex_block(nir_block *block, nir_builder *b,
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nir_lower_tex_block(nir_block *block, nir_builder *b,
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const nir_lower_tex_options *options)
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const nir_lower_tex_options *options)
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@@ -1135,6 +1176,11 @@ nir_lower_tex_block(nir_block *block, nir_builder *b,
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continue;
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continue;
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}
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}
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if (options->lower_txs_lod && tex->op == nir_texop_txs) {
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progress |= nir_lower_txs_lod(b, tex);
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continue;
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}
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/* has to happen after all the other lowerings as the original tg4 gets
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/* has to happen after all the other lowerings as the original tg4 gets
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* replaced by 4 tg4 instructions.
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* replaced by 4 tg4 instructions.
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*/
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*/
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