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Convert most remaining free-form fall-through comments to FALLTHROUGH

Browse Source 
One exception is src/amd/addrlib/, for which -Wimplicit-fallthrough is
explicitly disabled.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10220>
This commit is contained in:
Michel Dänzer
2021-04-10 17:11:58 +02:00
committed by Marge Bot
parent 96f0f46350
commit 2928c21eb7
147 changed files with 307 additions and 286 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/intel/compiler/brw_compile_sf.c
View File

@@ -167,9 +167,9 @@ static void do_twoside_color( struct brw_sf_compile *c )
brw_IF(p, BRW_EXECUTE_4);
{
switch (c->nr_verts) {
case 3: copy_bfc(c, c->vert[2]); /* fallthrough */
case 2: copy_bfc(c, c->vert[1]); /* fallthrough */
case 1: copy_bfc(c, c->vert[0]); /* fallthrough */
case 3: copy_bfc(c, c->vert[2]); FALLTHROUGH;
case 2: copy_bfc(c, c->vert[1]); FALLTHROUGH;
case 1: copy_bfc(c, c->vert[0]);
}
}
brw_ENDIF(p);

2
src/intel/compiler/brw_disasm.c
View File

@@ -2066,7 +2066,7 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP:
case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP:
format(file, "SIMD%d,", (msg_ctrl & (1 << 4)) ? 8 : 16);
/* fallthrough */
FALLTHROUGH;
case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2:
case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2:
case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2:

2
src/intel/compiler/brw_eu_emit.c
View File

@@ -2909,7 +2909,7 @@ brw_find_next_block_end(struct brw_codegen *p, int start_offset)
*/
if (!while_jumps_before_offset(devinfo, insn, offset, start_offset))
continue;
/* fallthrough */
FALLTHROUGH;
case BRW_OPCODE_ELSE:
case BRW_OPCODE_HALT:
if (depth == 0)

2
src/intel/compiler/brw_fs_builder.h
View File

@@ -822,7 +822,7 @@ namespace brw {
src.width != BRW_WIDTH_8 ||
src.hstride != BRW_HORIZONTAL_STRIDE_1)
break;
/* fallthrough */
FALLTHROUGH;
case ATTR:
case VGRF:
case UNIFORM:

4
src/intel/compiler/brw_fs_copy_propagation.cpp
View File

@@ -778,7 +778,7 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry)
/* FINISHME: Promote non-float constants and remove this. */
if (devinfo->ver < 8)
break;
/* fallthrough */
FALLTHROUGH;
case SHADER_OPCODE_POW:
/* Allow constant propagation into src1 (except on Gen 6 which
* doesn't support scalar source math), and let constant combining
@@ -786,7 +786,7 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry)
*/
if (devinfo->ver == 6)
break;
/* fallthrough */
FALLTHROUGH;
case BRW_OPCODE_BFI1:
case BRW_OPCODE_ASR:
case BRW_OPCODE_SHL:

2
src/intel/compiler/brw_fs_generator.cpp
View File

@@ -62,7 +62,7 @@ brw_reg_from_fs_reg(const struct gen_device_info *devinfo, fs_inst *inst,
switch (reg->file) {
case MRF:
assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->ver));
/* Fallthrough */
FALLTHROUGH;
case VGRF:
if (reg->stride == 0) {
brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);

10
src/intel/compiler/brw_fs_nir.cpp
View File

@@ -1049,7 +1049,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
break;
op[0].type = BRW_REGISTER_TYPE_D;
op[0].negate = !op[0].negate;
/* fallthrough */
FALLTHROUGH;
case nir_op_i2f64:
case nir_op_i2i64:
case nir_op_u2f64:
@@ -1174,7 +1174,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
bld.emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(),
brw_imm_d(rnd));
}
/* fallthrough */
FALLTHROUGH;
case nir_op_iadd:
inst = bld.ADD(result, op[0], op[1]);
break;
@@ -1624,7 +1624,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
case nir_op_unpack_half_2x16_split_x_flush_to_zero:
assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 & execution_mode);
/* Fall-through */
FALLTHROUGH;
case nir_op_unpack_half_2x16_split_x:
inst = bld.emit(BRW_OPCODE_F16TO32, result,
subscript(op[0], BRW_REGISTER_TYPE_UW, 0));
@@ -1632,7 +1632,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
case nir_op_unpack_half_2x16_split_y_flush_to_zero:
assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 & execution_mode);
/* Fall-through */
FALLTHROUGH;
case nir_op_unpack_half_2x16_split_y:
inst = bld.emit(BRW_OPCODE_F16TO32, result,
subscript(op[0], BRW_REGISTER_TYPE_UW, 1));
@@ -4255,7 +4255,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
case nir_intrinsic_scoped_barrier:
assert(nir_intrinsic_execution_scope(instr) == NIR_SCOPE_NONE);
/* Fall through. */
FALLTHROUGH;
case nir_intrinsic_group_memory_barrier:
case nir_intrinsic_memory_barrier_shared:
case nir_intrinsic_memory_barrier_buffer:

2
src/intel/compiler/brw_nir_lower_rt_intrinsics.c
View File

@@ -72,7 +72,7 @@ lower_rt_intrinsics_impl(nir_function_impl *impl,
stage == MESA_SHADER_CLOSEST_HIT);
brw_nir_rt_load_mem_ray(b, &object_ray_in,
BRW_RT_BVH_LEVEL_OBJECT);
/* Fall through */
FALLTHROUGH;
case MESA_SHADER_MISS:
brw_nir_rt_load_mem_ray(b, &world_ray_in,

2
src/intel/compiler/brw_shader.cpp
View File

@@ -871,7 +871,7 @@ backend_instruction::is_commutative() const
conditional_mod == BRW_CONDITIONAL_L) {
return true;
}
/* fallthrough */
FALLTHROUGH;
default:
return false;
}

2
src/intel/compiler/brw_vec4.cpp
View File

@@ -2066,7 +2066,7 @@ vec4_visitor::convert_to_hw_regs()
reg = src.as_brw_reg();
break;
}
/* fallthrough */
FALLTHROUGH;
case ARF:
case IMM:
continue;

16
src/intel/compiler/brw_vec4_nir.cpp
View File

@@ -699,7 +699,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
case nir_intrinsic_scoped_barrier:
assert(nir_intrinsic_execution_scope(instr) == NIR_SCOPE_NONE);
/* Fall through. */
FALLTHROUGH;
case nir_intrinsic_memory_barrier: {
const vec4_builder bld =
vec4_builder(this).at_end().annotate(current_annotation, base_ir);
@@ -1173,7 +1173,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
case nir_op_iadd:
assert(nir_dest_bit_size(instr->dest.dest) < 64);
/* fall through */
FALLTHROUGH;
case nir_op_fadd:
try_immediate_source(instr, op, true);
inst = emit(ADD(dst, op[0], op[1]));
@@ -1402,7 +1402,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
case nir_op_imin:
case nir_op_umin:
assert(nir_dest_bit_size(instr->dest.dest) < 64);
/* fall through */
FALLTHROUGH;
case nir_op_fmin:
try_immediate_source(instr, op, true);
inst = emit_minmax(BRW_CONDITIONAL_L, dst, op[0], op[1]);
@@ -1411,7 +1411,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
case nir_op_imax:
case nir_op_umax:
assert(nir_dest_bit_size(instr->dest.dest) < 64);
/* fall through */
FALLTHROUGH;
case nir_op_fmax:
try_immediate_source(instr, op, true);
inst = emit_minmax(BRW_CONDITIONAL_GE, dst, op[0], op[1]);
@@ -1432,7 +1432,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
case nir_op_ieq32:
case nir_op_ine32:
assert(nir_dest_bit_size(instr->dest.dest) < 64);
/* Fallthrough */
FALLTHROUGH;
case nir_op_flt32:
case nir_op_fge32:
case nir_op_feq32:
@@ -1467,7 +1467,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
case nir_op_b32all_iequal3:
case nir_op_b32all_iequal4:
assert(nir_dest_bit_size(instr->dest.dest) < 64);
/* Fallthrough */
FALLTHROUGH;
case nir_op_b32all_fequal2:
case nir_op_b32all_fequal3:
case nir_op_b32all_fequal4: {
@@ -1486,7 +1486,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
case nir_op_b32any_inequal3:
case nir_op_b32any_inequal4:
assert(nir_dest_bit_size(instr->dest.dest) < 64);
/* Fallthrough */
FALLTHROUGH;
case nir_op_b32any_fnequal2:
case nir_op_b32any_fnequal3:
case nir_op_b32any_fnequal4: {
@@ -1919,7 +1919,7 @@ vec4_visitor::nir_emit_jump(nir_jump_instr *instr)
break;
case nir_jump_return:
/* fall through */
FALLTHROUGH;
default:
unreachable("unknown jump");
}