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i965/fs/generator: refactor rounding mode helper in preparation for float controls

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v2:
- Fix bug in defining BRW_CR0_FP_MODE_MASK.

v3:
- Update comment (Caio).

v4:
- Split the patch into the helper (this one) and the new
  opcode (Caio).

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
This commit is contained in:
Samuel Iglesias Gonsálvez
2019-09-13 01:34:35 +03:00
committed by Andres Gomez
parent cdace5b0c6
commit 28da9558f5
3 changed files with 29 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/intel/compiler/brw_eu.h
View File

@@ -1145,8 +1145,8 @@ brw_broadcast(struct brw_codegen *p,
struct brw_reg idx);
void
brw_rounding_mode(struct brw_codegen *p,
enum brw_rnd_mode mode);
brw_float_controls_mode(struct brw_codegen *p,
unsigned mode, unsigned mask);
/***********************************************************************
* brw_eu_util.c:

26
src/intel/compiler/brw_eu_emit.c
View File

@@ -3476,21 +3476,12 @@ brw_WAIT(struct brw_codegen *p)
brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
}
/**
* Changes the floating point rounding mode updating the control register
* field defined at cr0.0[5-6] bits. This function supports the changes to
* RTNE (00), RU (01), RD (10) and RTZ (11) rounding using bitwise operations.
* Only RTNE and RTZ rounding are enabled at nir.
*/
void
brw_rounding_mode(struct brw_codegen *p,
enum brw_rnd_mode mode)
brw_float_controls_mode(struct brw_codegen *p,
unsigned mode, unsigned mask)
{
const unsigned bits = mode << BRW_CR0_RND_MODE_SHIFT;
if (bits != BRW_CR0_RND_MODE_MASK) {
brw_inst *inst = brw_AND(p, brw_cr0_reg(0), brw_cr0_reg(0),
brw_imm_ud(~BRW_CR0_RND_MODE_MASK));
brw_imm_ud(~mask));
brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1);
/* From the Skylake PRM, Volume 7, page 760:
@@ -3501,12 +3492,11 @@ brw_rounding_mode(struct brw_codegen *p,
* control register as an explicit operand."
*/
brw_inst_set_thread_control(p->devinfo, inst, BRW_THREAD_SWITCH);
}
if (bits) {
brw_inst *inst = brw_OR(p, brw_cr0_reg(0), brw_cr0_reg(0),
brw_imm_ud(bits));
brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1);
brw_inst_set_thread_control(p->devinfo, inst, BRW_THREAD_SWITCH);
if (mode) {
brw_inst *inst_or = brw_OR(p, brw_cr0_reg(0), brw_cr0_reg(0),
brw_imm_ud(mode));
brw_inst_set_exec_size(p->devinfo, inst_or, BRW_EXECUTE_1);
brw_inst_set_thread_control(p->devinfo, inst_or, BRW_THREAD_SWITCH);
}
}

11
src/intel/compiler/brw_fs_generator.cpp
View File

@@ -2218,9 +2218,16 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
break;
case SHADER_OPCODE_RND_MODE:
case SHADER_OPCODE_RND_MODE: {
assert(src[0].file == BRW_IMMEDIATE_VALUE);
brw_rounding_mode(p, (brw_rnd_mode) src[0].d);
/*
* Changes the floating point rounding mode updating the control
* register field defined at cr0.0[5-6] bits.
*/
enum brw_rnd_mode mode =
(enum brw_rnd_mode) (src[0].d << BRW_CR0_RND_MODE_SHIFT);
brw_float_controls_mode(p, mode, BRW_CR0_RND_MODE_MASK);
}
break;
default: