diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 3d144fa0429..48f48b22394 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3338,27 +3338,17 @@ VkResult radv_create_shaders(struct radv_pipeline *pipeline,
 
 	for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
 		const VkPipelineShaderStageCreateInfo *stage = pStages[i];
-		unsigned subgroup_size = 64, ballot_bit_size = 64;
 
 		if (!modules[i])
 			continue;
 
 		radv_start_feedback(stage_feedbacks[i]);
 
-		if (pipeline_key->compute_subgroup_size) {
-			/* Only compute shaders currently support requiring a
-			 * specific subgroup size.
-                         */
-			assert(i == MESA_SHADER_COMPUTE);
-			subgroup_size = pipeline_key->compute_subgroup_size;
-			ballot_bit_size = pipeline_key->compute_subgroup_size;
-		}
-
 		nir[i] = radv_shader_compile_to_nir(device, modules[i],
 						    stage ? stage->pName : "main", i,
 						    stage ? stage->pSpecializationInfo : NULL,
 						    flags, pipeline->layout,
-						    subgroup_size, ballot_bit_size);
+						    pipeline_key);
 
 		/* We don't want to alter meta shaders IR directly so clone it
 		 * first.
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 713cec0d299..17a3a51f297 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -288,7 +288,7 @@ mark_geom_invariant(nir_shader *nir)
 }
 
 static bool
-lower_intrinsics(nir_shader *nir)
+lower_intrinsics(nir_shader *nir, const struct radv_pipeline_key *key)
 {
 	nir_function_impl *entry = nir_shader_get_entrypoint(nir);
 	bool progress = false;
@@ -312,6 +312,9 @@ lower_intrinsics(nir_shader *nir)
 				def = nir_ieq_imm(&b, intrin->src[0].ssa, 0);
 			} else if (intrin->intrinsic == nir_intrinsic_sparse_residency_code_and) {
 				def = nir_ior(&b, intrin->src[0].ssa, intrin->src[1].ssa);
+			} else if (intrin->intrinsic == nir_intrinsic_load_view_index &&
+				   !key->has_multiview_view_index) {
+				def = nir_imm_zero(&b, 1, 32);
 			} else {
 				continue;
 			}
@@ -335,8 +338,18 @@ radv_shader_compile_to_nir(struct radv_device *device,
 			   const VkSpecializationInfo *spec_info,
 			   const VkPipelineCreateFlags flags,
 			   const struct radv_pipeline_layout *layout,
-			   unsigned subgroup_size, unsigned ballot_bit_size)
+			   const struct radv_pipeline_key *key)
 {
+	unsigned subgroup_size = 64, ballot_bit_size = 64;
+	if (key->compute_subgroup_size) {
+		/* Only compute shaders currently support requiring a
+		 * specific subgroup size.
+		 */
+		assert(stage == MESA_SHADER_COMPUTE);
+		subgroup_size = key->compute_subgroup_size;
+		ballot_bit_size = key->compute_subgroup_size;
+	}
+
 	nir_shader *nir;
 
 	if (module->nir) {
@@ -632,7 +645,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
 		   nir_var_mem_ubo | nir_var_mem_ssbo,
 		   nir_address_format_32bit_index_offset);
 
-	NIR_PASS_V(nir, lower_intrinsics);
+	NIR_PASS_V(nir, lower_intrinsics, key);
 
 	/* Lower deref operations for compute shared memory. */
 	if (nir->info.stage == MESA_SHADER_COMPUTE) {
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 79754ef89fb..7eed1ed60ce 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -432,7 +432,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
 			   const VkSpecializationInfo *spec_info,
 			   const VkPipelineCreateFlags flags,
 			   const struct radv_pipeline_layout *layout,
-			   unsigned subgroup_size, unsigned ballot_bit_size);
+			   const struct radv_pipeline_key *key);
 
 void
 radv_destroy_shader_slabs(struct radv_device *device);