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i965/blorp: Get rid of brw_blorp_surface_info::num_samples

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Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Jason Ekstrand
2016-06-23 11:00:59 -07:00
parent aa6c058ac4
commit 28b0ad890c
6 changed files with 31 additions and 35 deletions
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8
src/mesa/drivers/dri/i965/brw_blorp.c
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@@ -69,7 +69,6 @@ brw_blorp_surface_info_init(struct brw_context *brw,
intel_miptree_get_image_offset(mt, level, layer,
&info->x_offset, &info->y_offset);
info->num_samples = mt->num_samples;
info->array_layout = mt->array_layout;
info->msaa_layout = mt->msaa_layout;
info->swizzle = SWIZZLE_XYZW;
@@ -262,14 +261,13 @@ brw_blorp_emit_surface_state(struct brw_context *brw,
surf.logical_level0_px.depth = 1;
surf.logical_level0_px.array_len = 1;
surf.levels = 1;
surf.samples = MAX2(surface->num_samples, 1);
/* Alignment doesn't matter since we have 1 miplevel and 1 array slice so
* just pick something that works for everybody.
*/
surf.image_alignment_el = isl_extent3d(4, 4, 1);
if (brw->gen == 6 && surface->num_samples > 1) {
if (brw->gen == 6 && surf.samples > 1) {
/* Since gen6 uses INTEL_MSAA_LAYOUT_IMS, width and height are measured
* in samples. But SURFACE_STATE wants them in pixels, so we need to
* divide them each by 2.
@@ -524,8 +522,8 @@ gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
* not 8. But commit 1f112cc increased the alignment from 4 to 8, which
* prevents the clobbering.
*/
params.dst.num_samples = mt->num_samples;
if (params.dst.num_samples > 1) {
params.dst.surf.samples = MAX2(mt->num_samples, 1);
if (params.depth.surf.samples > 1) {
params.depth.width = ALIGN(mt->logical_width0, 8);
params.depth.height = ALIGN(mt->logical_height0, 4);
} else {

2
src/mesa/drivers/dri/i965/brw_blorp.h
View File

@@ -118,8 +118,6 @@ struct brw_blorp_surface_info
*/
uint32_t y_offset;
unsigned num_samples;
/**
* Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
* or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).

28
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
View File

@@ -1672,7 +1672,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
* R32_FLOAT, so only the contents of the red channel matters.
*/
if (brw->gen == 6 &&
params.src.num_samples > 1 && params.dst.num_samples <= 1 &&
params.src.surf.samples > 1 && params.dst.surf.samples <= 1 &&
src_mt->format == dst_mt->format &&
params.dst.brw_surfaceformat == BRW_SURFACEFORMAT_R32_FLOAT) {
params.src.brw_surfaceformat = params.dst.brw_surfaceformat;
@@ -1713,10 +1713,10 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
* single-sampled texture and interleave the samples ourselves.
*/
if (dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS)
params.dst.num_samples = 0;
params.dst.surf.samples = 1;
}
if (params.src.num_samples > 0 && params.dst.num_samples > 1) {
if (params.src.surf.samples > 0 && params.dst.surf.samples > 1) {
/* We are blitting from a multisample buffer to a multisample buffer, so
* we must preserve samples within a pixel. This means we have to
* arrange for the WM program to run once per sample rather than once
@@ -1740,7 +1740,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
wm_prog_key.y_scale = src_mt->num_samples / wm_prog_key.x_scale;
if (filter == GL_LINEAR &&
params.src.num_samples <= 1 && params.dst.num_samples <= 1)
params.src.surf.samples <= 1 && params.dst.surf.samples <= 1)
wm_prog_key.bilinear_filter = true;
GLenum base_format = _mesa_get_format_base_format(src_mt->format);
@@ -1767,17 +1767,17 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
/* tex_samples and rt_samples are the sample counts that are set up in
* SURFACE_STATE.
*/
wm_prog_key.tex_samples = params.src.num_samples;
wm_prog_key.rt_samples = params.dst.num_samples;
wm_prog_key.tex_samples = params.src.surf.samples;
wm_prog_key.rt_samples = params.dst.surf.samples;
/* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
* use to access the source and destination surfaces.
*/
wm_prog_key.tex_layout =
compute_msaa_layout_for_pipeline(brw, params.src.num_samples,
compute_msaa_layout_for_pipeline(brw, params.src.surf.samples,
params.src.msaa_layout);
wm_prog_key.rt_layout =
compute_msaa_layout_for_pipeline(brw, params.dst.num_samples,
compute_msaa_layout_for_pipeline(brw, params.dst.surf.samples,
params.dst.msaa_layout);
/* src_layout and dst_layout indicate the true MSAA layout used by src and
@@ -1792,10 +1792,10 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
* from compiler point of view. Therefore override the type in the program
* key.
*/
if (brw->gen >= 9 && params.src.num_samples <= 1 &&
if (brw->gen >= 9 && params.src.surf.samples <= 1 &&
src_mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS)
wm_prog_key.src_layout = INTEL_MSAA_LAYOUT_NONE;
if (brw->gen >= 9 && params.dst.num_samples <= 1 &&
if (brw->gen >= 9 && params.dst.surf.samples <= 1 &&
dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS)
wm_prog_key.dst_layout = INTEL_MSAA_LAYOUT_NONE;
@@ -1827,7 +1827,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
params.wm_inputs.src_z = 0;
}
if (params.dst.num_samples <= 1 && dst_mt->num_samples > 1) {
if (params.dst.surf.samples <= 1 && dst_mt->num_samples > 1) {
/* We must expand the rectangle we send through the rendering pipeline,
* to account for the fact that we are mapping the destination region as
* single-sampled when it is in fact multisampled. We must also align
@@ -1878,7 +1878,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
wm_prog_key.dst_tiled_w = true;
if (params.dst.num_samples > 1) {
if (params.dst.surf.samples > 1) {
/* If the destination surface is a W-tiled multisampled stencil
* buffer that we're mapping as Y tiled, then we need to arrange for
* the WM program to run once per sample rather than once per pixel,
@@ -1934,7 +1934,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
* TODO: what if this makes the coordinates (or the texture size) too
* large?
*/
const unsigned x_align = 8, y_align = params.dst.num_samples != 0 ? 8 : 4;
const unsigned x_align = 8, y_align = params.dst.surf.samples != 0 ? 8 : 4;
params.x0 = ROUND_DOWN_TO(params.x0, x_align) * 2;
params.y0 = ROUND_DOWN_TO(params.y0, y_align) / 2;
params.x1 = ALIGN(params.x1, x_align) * 2;
@@ -1963,7 +1963,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
*
* TODO: what if this makes the texture size too large?
*/
const unsigned x_align = 8, y_align = params.src.num_samples != 0 ? 8 : 4;
const unsigned x_align = 8, y_align = params.src.surf.samples != 0 ? 8 : 4;
params.src.width = ALIGN(params.src.width, x_align) * 2;
params.src.height = ALIGN(params.src.height, y_align) / 2;
params.src.x_offset *= 2;

10
src/mesa/drivers/dri/i965/gen6_blorp.c
View File

@@ -567,7 +567,7 @@ gen6_blorp_emit_sf_config(struct brw_context *brw,
BRW_SF_URB_ENTRY_READ_OFFSET <<
GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT);
OUT_BATCH(0); /* dw2 */
OUT_BATCH(params->dst.num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
OUT_BATCH(params->dst.surf.samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
for (int i = 0; i < 13; ++i)
OUT_BATCH(0);
OUT_BATCH(params->wm_prog_data ? params->wm_prog_data->flat_inputs : 0);
@@ -639,7 +639,7 @@ gen6_blorp_emit_wm_config(struct brw_context *brw,
dw2 |= 1 << GEN6_WM_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
}
if (params->dst.num_samples > 1) {
if (params->dst.surf.samples > 1) {
dw6 |= GEN6_WM_MSRAST_ON_PATTERN;
if (prog_data && prog_data->persample_msaa_dispatch)
dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE;
@@ -939,10 +939,10 @@ gen6_blorp_exec(struct brw_context *brw,
brw_upload_state_base_address(brw);
gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
gen6_emit_3dstate_multisample(brw, params->dst.surf.samples);
gen6_emit_3dstate_sample_mask(brw,
params->dst.num_samples > 1 ?
(1 << params->dst.num_samples) - 1 : 1);
params->dst.surf.samples > 1 ?
(1 << params->dst.surf.samples) - 1 : 1);
gen6_blorp_emit_vertices(brw, params);
gen6_blorp_emit_urb_config(brw, params);
if (params->wm_prog_data) {

10
src/mesa/drivers/dri/i965/gen7_blorp.c
View File

@@ -303,7 +303,7 @@ gen7_blorp_emit_sf_config(struct brw_context *brw,
OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
OUT_BATCH(params->depth_format <<
GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
OUT_BATCH(params->dst.num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
OUT_BATCH(params->dst.surf.samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
@@ -377,7 +377,7 @@ gen7_blorp_emit_wm_config(struct brw_context *brw,
if (params->src.mt)
dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
if (params->dst.num_samples > 1) {
if (params->dst.surf.samples > 1) {
dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
if (prog_data && prog_data->persample_msaa_dispatch)
dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
@@ -662,10 +662,10 @@ gen7_blorp_exec(struct brw_context *brw,
brw_upload_state_base_address(brw);
gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
gen6_emit_3dstate_multisample(brw, params->dst.surf.samples);
gen6_emit_3dstate_sample_mask(brw,
params->dst.num_samples > 1 ?
(1 << params->dst.num_samples) - 1 : 1);
params->dst.surf.samples > 1 ?
(1 << params->dst.surf.samples) - 1 : 1);
gen6_blorp_emit_vertices(brw, params);
gen7_blorp_emit_urb_config(brw, params);
if (params->wm_prog_data) {

8
src/mesa/drivers/dri/i965/gen8_blorp.c
View File

@@ -368,7 +368,7 @@ gen8_blorp_emit_ps_extra(struct brw_context *brw,
if (params->wm_prog_data->num_varying_inputs)
dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
if (params->dst.num_samples > 1 && prog_data &&
if (params->dst.surf.samples > 1 && prog_data &&
prog_data->persample_msaa_dispatch)
dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
@@ -593,10 +593,10 @@ gen8_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params)
gen7_blorp_emit_sampler_state_pointers_ps(brw, sampler_offset);
}
gen8_emit_3dstate_multisample(brw, params->dst.num_samples);
gen8_emit_3dstate_multisample(brw, params->dst.surf.samples);
gen6_emit_3dstate_sample_mask(brw,
params->dst.num_samples > 1 ?
(1 << params->dst.num_samples) - 1 : 1);
params->dst.surf.samples > 1 ?
(1 << params->dst.surf.samples) - 1 : 1);
gen8_disable_stages.emit(brw);
gen8_blorp_emit_vs_disable(brw);