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amd/vpelib: Refactor frontend and backend config callback

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Refactor and rename frontend and backend config callback.

Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Jack Chih <chiachih@amd.com>
Signed-off-by: Jesse Agate <Jesse.Agate@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30531>
This commit is contained in:
Agate, Jesse
2024-04-30 18:41:05 -04:00
committed by Marge Bot
parent 4886ee5caf
commit 282ad9d864
3 changed files with 62 additions and 55 deletions
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57
src/amd/vpelib/src/chip/vpe10/vpe10_resource.c
View File

@@ -680,39 +680,6 @@ static void build_clamping_params(
}
}
static void frontend_config_callback(
void *ctx, uint64_t cfg_base_gpu, uint64_t cfg_base_cpu, uint64_t size)
{
struct config_frontend_cb_ctx *cb_ctx = (struct config_frontend_cb_ctx *)ctx;
struct vpe_priv *vpe_priv = cb_ctx->vpe_priv;
struct stream_ctx *stream_ctx = &vpe_priv->stream_ctx[cb_ctx->stream_idx];
enum vpe_cmd_type cmd_type;
if (cb_ctx->stream_sharing) {
VPE_ASSERT(stream_ctx->num_configs <
(int)(sizeof(stream_ctx->configs) / sizeof(struct config_record)));
stream_ctx->configs[stream_ctx->num_configs].config_base_addr = cfg_base_gpu;
stream_ctx->configs[stream_ctx->num_configs].config_size = size;
stream_ctx->num_configs++;
} else if (cb_ctx->stream_op_sharing) {
cmd_type = cb_ctx->cmd_type;
VPE_ASSERT(
stream_ctx->num_stream_op_configs[cmd_type] <
(int)(sizeof(stream_ctx->stream_op_configs[cmd_type]) / sizeof(struct config_record)));
stream_ctx->stream_op_configs[cmd_type][stream_ctx->num_stream_op_configs[cmd_type]]
.config_base_addr = cfg_base_gpu;
stream_ctx->stream_op_configs[cmd_type][stream_ctx->num_stream_op_configs[cmd_type]]
.config_size = size;
stream_ctx->num_stream_op_configs[cmd_type]++;
}
vpe_desc_writer_add_config_desc(
&vpe_priv->vpe_desc_writer, cfg_base_gpu, false, vpe_priv->config_writer.buf->tmz);
}
int32_t vpe10_program_frontend(struct vpe_priv *vpe_priv, uint32_t pipe_idx, uint32_t cmd_idx,
uint32_t cmd_input_idx, bool seg_only)
{
@@ -731,7 +698,7 @@ int32_t vpe10_program_frontend(struct vpe_priv *vpe_priv, uint32_t pipe_idx, uin
vpe_priv->fe_cb_ctx.vpe_priv = vpe_priv;
config_writer_set_callback(
&vpe_priv->config_writer, &vpe_priv->fe_cb_ctx, frontend_config_callback);
&vpe_priv->config_writer, &vpe_priv->fe_cb_ctx, vpe_frontend_config_callback);
config_writer_set_type(&vpe_priv->config_writer, CONFIG_TYPE_DIRECT);
@@ -806,26 +773,6 @@ int32_t vpe10_program_frontend(struct vpe_priv *vpe_priv, uint32_t pipe_idx, uin
return 0;
}
static void backend_config_callback(
void *ctx, uint64_t cfg_base_gpu, uint64_t cfg_base_cpu, uint64_t size)
{
struct config_backend_cb_ctx *cb_ctx = (struct config_backend_cb_ctx *)ctx;
struct vpe_priv *vpe_priv = cb_ctx->vpe_priv;
struct output_ctx *output_ctx = &vpe_priv->output_ctx;
if (cb_ctx->share) {
VPE_ASSERT(
output_ctx->num_configs < (sizeof(output_ctx->configs) / sizeof(struct config_record)));
output_ctx->configs[output_ctx->num_configs].config_base_addr = cfg_base_gpu;
output_ctx->configs[output_ctx->num_configs].config_size = size;
output_ctx->num_configs++;
}
vpe_desc_writer_add_config_desc(
&vpe_priv->vpe_desc_writer, cfg_base_gpu, false, vpe_priv->config_writer.buf->tmz);
}
int32_t vpe10_program_backend(
struct vpe_priv *vpe_priv, uint32_t pipe_idx, uint32_t cmd_idx, bool seg_only)
{
@@ -844,7 +791,7 @@ int32_t vpe10_program_backend(
vpe_priv->be_cb_ctx.vpe_priv = vpe_priv;
config_writer_set_callback(
&vpe_priv->config_writer, &vpe_priv->be_cb_ctx, backend_config_callback);
&vpe_priv->config_writer, &vpe_priv->be_cb_ctx, vpe_backend_config_callback);
config_writer_set_type(&vpe_priv->config_writer, CONFIG_TYPE_DIRECT);

7
src/amd/vpelib/src/core/inc/resource.h
View File

@@ -152,6 +152,13 @@ void vpe_handle_output_h_mirror(struct vpe_priv *vpe_priv);
void vpe_resource_build_bit_depth_reduction_params(
struct opp *opp, struct bit_depth_reduction_params *fmt_bit_depth);
/** resource function call backs*/
void vpe_frontend_config_callback(
void *ctx, uint64_t cfg_base_gpu, uint64_t cfg_base_cpu, uint64_t size);
void vpe_backend_config_callback(
void *ctx, uint64_t cfg_base_gpu, uint64_t cfg_base_cpu, uint64_t size);
#ifdef __cplusplus
}
#endif

53
src/amd/vpelib/src/core/resource.c
View File

@@ -683,3 +683,56 @@ void vpe_resource_build_bit_depth_reduction_params(
break;
}
}
void vpe_frontend_config_callback(
void *ctx, uint64_t cfg_base_gpu, uint64_t cfg_base_cpu, uint64_t size)
{
struct config_frontend_cb_ctx *cb_ctx = (struct config_frontend_cb_ctx*)ctx;
struct vpe_priv *vpe_priv = cb_ctx->vpe_priv;
struct stream_ctx *stream_ctx = &vpe_priv->stream_ctx[cb_ctx->stream_idx];
enum vpe_cmd_type cmd_type;
if (cb_ctx->stream_sharing) {
VPE_ASSERT(stream_ctx->num_configs <
(int)(sizeof(stream_ctx->configs) / sizeof(struct config_record)));
stream_ctx->configs[stream_ctx->num_configs].config_base_addr = cfg_base_gpu;
stream_ctx->configs[stream_ctx->num_configs].config_size = size;
stream_ctx->num_configs++;
} else if (cb_ctx->stream_op_sharing) {
cmd_type = cb_ctx->cmd_type;
VPE_ASSERT(
stream_ctx->num_stream_op_configs[cmd_type] <
(int)(sizeof(stream_ctx->stream_op_configs[cmd_type]) / sizeof(struct config_record)));
stream_ctx->stream_op_configs[cmd_type][stream_ctx->num_stream_op_configs[cmd_type]]
.config_base_addr = cfg_base_gpu;
stream_ctx->stream_op_configs[cmd_type][stream_ctx->num_stream_op_configs[cmd_type]]
.config_size = size;
stream_ctx->num_stream_op_configs[cmd_type]++;
}
vpe_desc_writer_add_config_desc(
&vpe_priv->vpe_desc_writer, cfg_base_gpu, false, vpe_priv->config_writer.buf->tmz);
}
void vpe_backend_config_callback(
void *ctx, uint64_t cfg_base_gpu, uint64_t cfg_base_cpu, uint64_t size)
{
struct config_backend_cb_ctx *cb_ctx = (struct config_backend_cb_ctx*)ctx;
struct vpe_priv *vpe_priv = cb_ctx->vpe_priv;
struct output_ctx *output_ctx = &vpe_priv->output_ctx;
if (cb_ctx->share) {
VPE_ASSERT(
output_ctx->num_configs < (sizeof(output_ctx->configs) / sizeof(struct config_record)));
output_ctx->configs[output_ctx->num_configs].config_base_addr = cfg_base_gpu;
output_ctx->configs[output_ctx->num_configs].config_size = size;
output_ctx->num_configs++;
}
vpe_desc_writer_add_config_desc(
&vpe_priv->vpe_desc_writer, cfg_base_gpu, false, vpe_priv->config_writer.buf->tmz);
}