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radv: Make FragCoord a sysval

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load_fragcoord is already handled in common code for radeonsi, so we
don't need to do anything to handle it. However, there were some passes
creating NIR with the varying, so we switch them over to the sysval. In
the case of nir_lower_input_attachments which is used by both radv and
anv, we add handling for both until intel switches to using a sysval.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Connor Abbott
2019-05-13 15:39:54 +02:00
parent 64f3fc5ea6
commit 27f0c3c15e
6 changed files with 14 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
src/amd/vulkan/radv_meta_resolve_fs.c
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@@ -55,7 +55,6 @@ build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, int samp
{ {
nir_builder b; nir_builder b;
char name[64]; char name[64];
const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
const struct glsl_type *vec4 = glsl_vec4_type(); const struct glsl_type *vec4 = glsl_vec4_type();
const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS, const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS,
false, false,
@@ -71,14 +70,11 @@ build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, int samp
input_img->data.descriptor_set = 0; input_img->data.descriptor_set = 0;
input_img->data.binding = 0; input_img->data.binding = 0;
nir_variable *fs_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "fs_pos_in");
fs_pos_in->data.location = VARYING_SLOT_POS;
nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out, nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
vec4, "f_color"); vec4, "f_color");
color_out->data.location = FRAG_RESULT_DATA0; color_out->data.location = FRAG_RESULT_DATA0;
nir_ssa_def *pos_in = nir_load_var(&b, fs_pos_in); nir_ssa_def *pos_in = nir_channels(&b, nir_load_frag_coord(&b), 0x3);
nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant); nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(src_offset, 0); nir_intrinsic_set_base(src_offset, 0);
nir_intrinsic_set_range(src_offset, 8); nir_intrinsic_set_range(src_offset, 8);
@@ -345,7 +341,6 @@ build_depth_stencil_resolve_fragment_shader(struct radv_device *dev, int samples
{ {
nir_builder b; nir_builder b;
char name[64]; char name[64];
const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
const struct glsl_type *vec4 = glsl_vec4_type(); const struct glsl_type *vec4 = glsl_vec4_type();
const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_2D, const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_2D,
false, false,
@@ -364,16 +359,13 @@ build_depth_stencil_resolve_fragment_shader(struct radv_device *dev, int samples
input_img->data.descriptor_set = 0; input_img->data.descriptor_set = 0;
input_img->data.binding = 0; input_img->data.binding = 0;
nir_variable *fs_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "fs_pos_in");
fs_pos_in->data.location = VARYING_SLOT_POS;
nir_variable *fs_out = nir_variable_create(b.shader, nir_variable *fs_out = nir_variable_create(b.shader,
nir_var_shader_out, vec4, nir_var_shader_out, vec4,
"f_out"); "f_out");
fs_out->data.location = fs_out->data.location =
index == DEPTH_RESOLVE ? FRAG_RESULT_DEPTH : FRAG_RESULT_STENCIL; index == DEPTH_RESOLVE ? FRAG_RESULT_DEPTH : FRAG_RESULT_STENCIL;
nir_ssa_def *pos_in = nir_load_var(&b, fs_pos_in); nir_ssa_def *pos_in = nir_channels(&b, nir_load_frag_coord(&b), 0x3);
nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant); nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(src_offset, 0); nir_intrinsic_set_base(src_offset, 0);

6
src/amd/vulkan/radv_nir_to_llvm.c
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@@ -2516,12 +2516,6 @@ handle_fs_inputs(struct radv_shader_context *ctx,
ctx->abi.prim_mask, false, inputs); ctx->abi.prim_mask, false, inputs);
++index; ++index;
} }
} else if (i == VARYING_SLOT_POS) {
for(int i = 0; i < 3; ++i)
inputs[i] = ctx->abi.frag_pos[i];
inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
ctx->abi.frag_pos[3]);
} }
} }
ctx->shader_info->fs.num_interp = index; ctx->shader_info->fs.num_interp = index;

3
src/amd/vulkan/radv_shader.c
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@@ -290,6 +290,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
.phys_ssbo_addr_format = nir_address_format_64bit_global, .phys_ssbo_addr_format = nir_address_format_64bit_global,
.push_const_addr_format = nir_address_format_logical, .push_const_addr_format = nir_address_format_logical,
.shared_addr_format = nir_address_format_32bit_offset, .shared_addr_format = nir_address_format_32bit_offset,
.frag_coord_is_sysval = true,
}; };
nir = spirv_to_nir(spirv, module->size / 4, nir = spirv_to_nir(spirv, module->size / 4,
spec_entries, num_spec_entries, spec_entries, num_spec_entries,
@@ -335,7 +336,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
NIR_PASS_V(nir, nir_split_per_member_structs); NIR_PASS_V(nir, nir_split_per_member_structs);
if (nir->info.stage == MESA_SHADER_FRAGMENT) if (nir->info.stage == MESA_SHADER_FRAGMENT)
NIR_PASS_V(nir, nir_lower_input_attachments); NIR_PASS_V(nir, nir_lower_input_attachments, true);
NIR_PASS_V(nir, nir_remove_dead_variables, NIR_PASS_V(nir, nir_remove_dead_variables,
nir_var_shader_in | nir_var_shader_out | nir_var_system_value); nir_var_shader_in | nir_var_shader_out | nir_var_system_value);

2
src/compiler/nir/nir.h
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@@ -3494,7 +3494,7 @@ bool nir_lower_non_uniform_access(nir_shader *shader,
bool nir_lower_idiv(nir_shader *shader); bool nir_lower_idiv(nir_shader *shader);
bool nir_lower_input_attachments(nir_shader *shader); bool nir_lower_input_attachments(nir_shader *shader, bool use_fragcoord_sysval);
bool nir_lower_clip_vs(nir_shader *shader, unsigned ucp_enables, bool use_vars); bool nir_lower_clip_vs(nir_shader *shader, unsigned ucp_enables, bool use_vars);
bool nir_lower_clip_fs(nir_shader *shader, unsigned ucp_enables); bool nir_lower_clip_fs(nir_shader *shader, unsigned ucp_enables);

12
src/compiler/nir/nir_lower_input_attachments.c
View File

@@ -48,7 +48,8 @@ load_frag_coord(nir_builder *b)
} }
static bool static bool
try_lower_input_load(nir_function_impl *impl, nir_intrinsic_instr *load) try_lower_input_load(nir_function_impl *impl, nir_intrinsic_instr *load,
bool use_fragcoord_sysval)
{ {
nir_deref_instr *deref = nir_src_as_deref(load->src[0]); nir_deref_instr *deref = nir_src_as_deref(load->src[0]);
assert(glsl_type_is_image(deref->type)); assert(glsl_type_is_image(deref->type));
@@ -64,7 +65,9 @@ try_lower_input_load(nir_function_impl *impl, nir_intrinsic_instr *load)
nir_builder_init(&b, impl); nir_builder_init(&b, impl);
b.cursor = nir_instr_remove(&load->instr); b.cursor = nir_instr_remove(&load->instr);
nir_ssa_def *frag_coord = nir_f2i32(&b, load_frag_coord(&b)); nir_ssa_def *frag_coord = use_fragcoord_sysval ? nir_load_frag_coord(&b)
: load_frag_coord(&b);
frag_coord = nir_f2i32(&b, frag_coord);
nir_ssa_def *offset = nir_ssa_for_src(&b, load->src[1], 2); nir_ssa_def *offset = nir_ssa_for_src(&b, load->src[1], 2);
nir_ssa_def *pos = nir_iadd(&b, frag_coord, offset); nir_ssa_def *pos = nir_iadd(&b, frag_coord, offset);
@@ -122,7 +125,7 @@ try_lower_input_load(nir_function_impl *impl, nir_intrinsic_instr *load)
} }
bool bool
nir_lower_input_attachments(nir_shader *shader) nir_lower_input_attachments(nir_shader *shader, bool use_fragcoord_sysval)
{ {
assert(shader->info.stage == MESA_SHADER_FRAGMENT); assert(shader->info.stage == MESA_SHADER_FRAGMENT);
bool progress = false; bool progress = false;
@@ -141,7 +144,8 @@ nir_lower_input_attachments(nir_shader *shader)
if (load->intrinsic != nir_intrinsic_image_deref_load) if (load->intrinsic != nir_intrinsic_image_deref_load)
continue; continue;
progress |= try_lower_input_load(function->impl, load); progress |= try_lower_input_load(function->impl, load,
use_fragcoord_sysval);
} }
} }
} }

2
src/intel/vulkan/anv_pipeline.c
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@@ -607,7 +607,7 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
if (nir->info.stage == MESA_SHADER_FRAGMENT) { if (nir->info.stage == MESA_SHADER_FRAGMENT) {
NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable); NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable);
NIR_PASS_V(nir, nir_lower_input_attachments); NIR_PASS_V(nir, nir_lower_input_attachments, false);
} }
NIR_PASS_V(nir, anv_nir_lower_ycbcr_textures, layout); NIR_PASS_V(nir, anv_nir_lower_ycbcr_textures, layout);