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nir/fold_16bit_sampler_conversions: add a mask for supported sampler dims

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AMD might not support cubes, but that doesn't mean cubes can't be used
on other drivers

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15852>
This commit is contained in:
Mike Blumenkrantz
2022-04-11 08:52:24 -04:00
committed by Marge Bot
parent 324b2ae5f2
commit 27a43b531b
4 changed files with 13 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/amd/vulkan/radv_pipeline.c
View File

@@ -4485,10 +4485,13 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
}
if (((stages[i].nir->info.bit_sizes_int | stages[i].nir->info.bit_sizes_float) & 16) &&
device->physical_device->rad_info.chip_class >= GFX9) {
uint32_t sampler_dims = UINT32_MAX;
/* Skip because AMD doesn't support 16-bit types with these. */
sampler_dims &= ~BITFIELD_BIT(GLSL_SAMPLER_DIM_CUBE);
// TODO: also optimize the tex srcs. see radeonSI for reference */
/* Skip if there are potentially conflicting rounding modes */
if (!nir_has_any_rounding_mode_enabled(stages[i].nir->info.float_controls_execution_mode))
NIR_PASS_V(stages[i].nir, nir_fold_16bit_sampler_conversions, 0);
NIR_PASS_V(stages[i].nir, nir_fold_16bit_sampler_conversions, 0, sampler_dims);
NIR_PASS_V(stages[i].nir, nir_opt_vectorize, opt_vectorize_callback, NULL);
}

2
src/compiler/nir/nir.h
View File

@@ -5219,7 +5219,7 @@ bool nir_force_mediump_io(nir_shader *nir, nir_variable_mode modes,
nir_alu_type types);
bool nir_unpack_16bit_varying_slots(nir_shader *nir, nir_variable_mode modes);
bool nir_fold_16bit_sampler_conversions(nir_shader *nir,
unsigned tex_src_types);
unsigned tex_src_types, uint32_t sampler_dims);
typedef struct {
bool legalize_type; /* whether this src should be legalized */

6
src/compiler/nir/nir_lower_mediump.c
View File

@@ -422,7 +422,8 @@ replace_with_mov(nir_builder *b, nir_instr *instr, nir_src *src,
*/
bool
nir_fold_16bit_sampler_conversions(nir_shader *nir,
unsigned tex_src_types)
unsigned tex_src_types,
uint32_t sampler_dims)
{
bool changed = false;
nir_function_impl *impl = nir_shader_get_entrypoint(nir);
@@ -444,10 +445,9 @@ nir_fold_16bit_sampler_conversions(nir_shader *nir,
if (tex->is_sparse)
continue;
/* Skip because AMD doesn't support 16-bit types with these. */
if ((tex->op == nir_texop_txs ||
tex->op == nir_texop_query_levels) ||
tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
!(sampler_dims & BITFIELD_BIT(tex->sampler_dim)))
continue;
/* Optimize source operands. */

6
src/gallium/drivers/radeonsi/si_shader_nir.c
View File

@@ -166,9 +166,13 @@ static void si_late_optimize_16bit_samplers(struct si_screen *sscreen, nir_shade
};
bool changed = false;
uint32_t sampler_dims = UINT32_MAX;
/* Skip because AMD doesn't support 16-bit types with these. */
sampler_dims &= ~BITFIELD_BIT(GLSL_SAMPLER_DIM_CUBE);
NIR_PASS(changed, nir, nir_fold_16bit_sampler_conversions,
(1 << nir_tex_src_coord) |
(has_g16 ? 1 << nir_tex_src_ddx : 0));
(has_g16 ? 1 << nir_tex_src_ddx : 0),
sampler_dims);
NIR_PASS(changed, nir, nir_legalize_16bit_sampler_srcs, tex_constraints);
if (changed) {