st/glsl_to_nir/radeonsi: enable gs support for nir backend
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
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@@ -227,7 +227,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_GLSL_FEATURE_LEVEL:
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if (sscreen->debug_flags & DBG(NIR))
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return 140; /* no geometry and tessellation shaders yet */
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return 150; /* no tessellation shaders yet */
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if (si_have_tgsi_compute(sscreen))
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return 450;
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return 420;
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@@ -452,6 +452,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
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case PIPE_SHADER_CAP_PREFERRED_IR:
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if (sscreen->debug_flags & DBG(NIR) &&
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(shader == PIPE_SHADER_VERTEX ||
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shader == PIPE_SHADER_GEOMETRY ||
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shader == PIPE_SHADER_FRAGMENT))
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return PIPE_SHADER_IR_NIR;
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return PIPE_SHADER_IR_TGSI;
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@@ -130,6 +130,7 @@ void si_nir_scan_shader(const struct nir_shader *nir,
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unsigned i;
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assert(nir->info.stage == MESA_SHADER_VERTEX ||
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nir->info.stage == MESA_SHADER_GEOMETRY ||
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nir->info.stage == MESA_SHADER_FRAGMENT);
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info->processor = pipe_shader_type_from_mesa(nir->info.stage);
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@@ -151,8 +152,6 @@ void si_nir_scan_shader(const struct nir_shader *nir,
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unsigned attrib_count = glsl_count_attribute_slots(variable->type,
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nir->info.stage == MESA_SHADER_VERTEX);
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assert(attrib_count == 1 && "not implemented");
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/* Vertex shader inputs don't have semantics. The state
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* tracker has already mapped them to attributes via
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* variable->data.driver_location.
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@@ -160,6 +159,9 @@ void si_nir_scan_shader(const struct nir_shader *nir,
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if (nir->info.stage == MESA_SHADER_VERTEX)
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continue;
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assert(nir->info.stage != MESA_SHADER_FRAGMENT ||
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(attrib_count == 1 && "not implemented"));
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/* Fragment shader position is a system value. */
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if (nir->info.stage == MESA_SHADER_FRAGMENT &&
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variable->data.location == VARYING_SLOT_POS) {
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@@ -559,6 +561,8 @@ bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
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{
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struct tgsi_shader_info *info = &ctx->shader->selector->info;
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if (nir->info.stage == MESA_SHADER_VERTEX ||
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nir->info.stage == MESA_SHADER_FRAGMENT) {
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uint64_t processed_inputs = 0;
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nir_foreach_variable(variable, &nir->inputs) {
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unsigned attrib_count = glsl_count_attribute_slots(variable->type,
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@@ -587,6 +591,7 @@ bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
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}
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processed_inputs |= ((uint64_t)1 << loc);
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}
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}
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ctx->abi.inputs = &ctx->inputs[0];
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ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
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@@ -650,6 +650,18 @@ st_finalize_nir(struct st_context *st, struct gl_program *prog,
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/* Re-lower global vars, to deal with any dead VS inputs. */
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NIR_PASS_V(nir, nir_lower_global_vars_to_local);
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sort_varyings(&nir->outputs);
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st_nir_assign_var_locations(&nir->outputs,
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&nir->num_outputs,
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nir->info.stage);
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st_nir_fixup_varying_slots(st, &nir->outputs);
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} else if (nir->info.stage == MESA_SHADER_GEOMETRY) {
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sort_varyings(&nir->inputs);
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st_nir_assign_var_locations(&nir->inputs,
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&nir->num_inputs,
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nir->info.stage);
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st_nir_fixup_varying_slots(st, &nir->inputs);
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sort_varyings(&nir->outputs);
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st_nir_assign_var_locations(&nir->outputs,
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&nir->num_outputs,
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