From 27314718a34d420b7f36eeefce22ee06919cdbed Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Tue, 17 May 2022 16:37:35 -0700 Subject: [PATCH] intel: Drop Wa_1409226450 (stall before instruction cache invalidation) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Production Tigerlake and DG1 hardware shouldn't need this workaround. It was only needed on the very first steppings which never went public. Reviewed-by: Tapani Pälli Part-of: --- src/gallium/drivers/iris/iris_state.c | 12 ------------ src/intel/vulkan/genX_cmd_buffer.c | 6 ------ 2 files changed, 18 deletions(-) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 09500e4085e..24dae802611 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -7810,18 +7810,6 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, 0, NULL, 0, 0); } - /* Wa_1409226450, Wait for EU to be idle before pipe control which - * invalidates the instruction cache - */ - if (GFX_VER == 12 && (flags & PIPE_CONTROL_INSTRUCTION_INVALIDATE)) { - iris_emit_raw_pipe_control(batch, - "workaround: CS stall before instruction " - "cache invalidate", - PIPE_CONTROL_CS_STALL | - PIPE_CONTROL_STALL_AT_SCOREBOARD, bo, offset, - imm); - } - if (GFX_VER == 9 && IS_COMPUTE_PIPELINE(batch) && post_sync_flags) { /* Project: SKL / Argument: LRI Post Sync Operation [23] * diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 089677e62fb..3d249d09aef 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -2132,12 +2132,6 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch, bits &= ~ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT; } - /* Wa_1409226450, Wait for EU to be idle before pipe control which - * invalidates the instruction cache - */ - if (GFX_VER == 12 && (bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)) - bits |= ANV_PIPE_CS_STALL_BIT | ANV_PIPE_STALL_AT_SCOREBOARD_BIT; - /* Project: SKL / Argument: LRI Post Sync Operation [23] * * "PIPECONTROL command with “Command Streamer Stall Enable” must be