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intel: Drop Wa_1409226450 (stall before instruction cache invalidation)

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Production Tigerlake and DG1 hardware shouldn't need this workaround.
It was only needed on the very first steppings which never went public.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16575>
This commit is contained in:
Kenneth Graunke
2022-05-17 16:37:35 -07:00
committed by Marge Bot
parent 7938ce4af3
commit 27314718a3
2 changed files with 0 additions and 18 deletions
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12
src/gallium/drivers/iris/iris_state.c
View File

@@ -7810,18 +7810,6 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
0, NULL, 0, 0);
}
/* Wa_1409226450, Wait for EU to be idle before pipe control which
* invalidates the instruction cache
*/
if (GFX_VER == 12 && (flags & PIPE_CONTROL_INSTRUCTION_INVALIDATE)) {
iris_emit_raw_pipe_control(batch,
"workaround: CS stall before instruction "
"cache invalidate",
PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_STALL_AT_SCOREBOARD, bo, offset,
imm);
}
if (GFX_VER == 9 && IS_COMPUTE_PIPELINE(batch) && post_sync_flags) {
/* Project: SKL / Argument: LRI Post Sync Operation [23]
*

6
src/intel/vulkan/genX_cmd_buffer.c
View File

@@ -2132,12 +2132,6 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
bits &= ~ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT;
}
/* Wa_1409226450, Wait for EU to be idle before pipe control which
* invalidates the instruction cache
*/
if (GFX_VER == 12 && (bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT))
bits |= ANV_PIPE_CS_STALL_BIT | ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
/* Project: SKL / Argument: LRI Post Sync Operation [23]
*
* "PIPECONTROL command with “Command Streamer Stall Enable” must be