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intel/fs: Disable 3-src immediates on XeHP.

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Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>

[ Francisco Jerez: Add TODO comment explaining why this is helpful and
  how we could better fix it. ]

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
This commit is contained in:
Jordan Justen
2021-04-06 13:11:09 -07:00
committed by Marge Bot
parent 02ce55d2b1
commit 262cb08557
1 changed files with 4 additions and 2 deletions
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6
src/intel/compiler/brw_fs_combine_constants.cpp
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@@ -339,8 +339,10 @@ static bool
represent_src_as_imm(const struct gen_device_info *devinfo, represent_src_as_imm(const struct gen_device_info *devinfo,
fs_reg *src) fs_reg *src)
{ {
/* TODO : consider specific platforms also */ /* TODO - Fix the codepath below to use a bfloat16 immediate on XeHP,
if (devinfo->ver == 12) { * since HF/F mixed mode has been removed from the hardware.
*/
if (devinfo->ver == 12 && devinfo->verx10 < 125) {
uint16_t hf; uint16_t hf;
if (representable_as_hf(src->f, &hf)) { if (representable_as_hf(src->f, &hf)) {
*src = retype(brw_imm_uw(hf), BRW_REGISTER_TYPE_HF); *src = retype(brw_imm_uw(hf), BRW_REGISTER_TYPE_HF);