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intel/compiler: Remove Gen10-specific code

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Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6899>
This commit is contained in:
Ian Romanick
2020-09-24 11:31:13 -07:00
parent e22f106e01
commit 262ca98b3a
8 changed files with 7 additions and 47 deletions
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7
src/intel/compiler/brw_shader.cpp
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@@ -1299,13 +1299,6 @@ brw_compile_tes(const struct brw_compiler *compiler,
/* URB entry sizes are stored as a multiple of 64 bytes. */
prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
/* On Cannonlake software shall not program an allocation size that
* specifies a size that is a multiple of 3 64B (512-bit) cachelines.
*/
if (devinfo->gen == 10 &&
prog_data->base.urb_entry_size % 3 == 0)
prog_data->base.urb_entry_size++;
prog_data->base.urb_read_length = 0;
STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);