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intel/compiler: Store Primitive ID in TCS thread payload struct

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Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
This commit is contained in:
Caio Oliveira
2022-08-19 15:04:15 -07:00
committed by Marge Bot
parent 9a9b1119b4
commit 2622fc3af1
3 changed files with 12 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/intel/compiler/brw_fs.h
View File

@@ -97,6 +97,7 @@ struct tcs_thread_payload : public thread_payload {
tcs_thread_payload(const fs_visitor &v);
fs_reg patch_urb_output;
fs_reg primitive_id;
};
struct fs_thread_payload : public thread_payload {

15
src/intel/compiler/brw_fs_nir.cpp
View File

@@ -2810,17 +2810,13 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(prog_data);
struct brw_vue_prog_data *vue_prog_data = &tcs_prog_data->base;
bool multi_patch =
vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH;
fs_reg dst;
if (nir_intrinsic_infos[instr->intrinsic].has_dest)
dst = get_nir_dest(instr->dest);
switch (instr->intrinsic) {
case nir_intrinsic_load_primitive_id:
bld.MOV(dst, fs_reg(multi_patch ? brw_vec8_grf(2, 0)
: brw_vec1_grf(0, 1)));
bld.MOV(dst, tcs_payload().primitive_id);
break;
case nir_intrinsic_load_invocation_id:
bld.MOV(retype(dst, invocation_id.type), invocation_id);
@@ -2847,9 +2843,12 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
unsigned imm_offset = nir_intrinsic_base(instr);
fs_inst *inst;
fs_reg icp_handle =
multi_patch ? get_tcs_multi_patch_icp_handle(bld, instr)
: get_tcs_single_patch_icp_handle(bld, instr);
const bool multi_patch =
vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH;
fs_reg icp_handle = multi_patch ?
get_tcs_multi_patch_icp_handle(bld, instr) :
get_tcs_single_patch_icp_handle(bld, instr);
/* We can only read two double components with each URB read, so
* we send two read messages in that case, each one loading up to

4
src/intel/compiler/brw_fs_thread_payload.cpp
View File

@@ -33,6 +33,7 @@ tcs_thread_payload::tcs_thread_payload(const fs_visitor &v)
if (vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH) {
patch_urb_output = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD);
primitive_id = brw_vec1_grf(0, 1);
/* r1-r4 contain the ICP handles. */
num_regs = 5;
@@ -42,6 +43,9 @@ tcs_thread_payload::tcs_thread_payload(const fs_visitor &v)
patch_urb_output = retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD);
if (tcs_prog_data->include_primitive_id)
primitive_id = brw_vec8_grf(2, 0);
/* r1 contains output handles, r2 may contain primitive ID, then the
* ICP handles occupy the next 1-32 registers.
*/